Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

Abstract: An aspect includes generating, within a first memory device of a memory system, a plurality of event-based information associated with activity in the memory system. The event-based information is stored in a reserved portion of the first memory device. The event-based information is provided to a memory controller of the memory system corresponding with an access of a memory row across a plurality of memory devices of the memory system associated with the event-based information.

Abstract: An aspect includes providing communication links from a memory controller to contents of a plurality of bit locations in a plurality of memory devices. A failing bit location in the plurality of bit locations is detected by the memory controller. A replacement bit location for the failing bit location is selected and a replacement communication link to the replacement bit location is provided by the memory controller. A request to access contents of the failing bit location received after the selecting and providing the replacement communication link is performed by accessing contents of the replacement bit location via the replacement communication link.

Abstract: A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an initial command, address, control (CAC) check with a CAC delay indicated as passing. Responsive to the initial read check, the initial write check, and the initial CAC check indicated as passing, for each setting of the read delay, the write delay, and the CAC delay, the calibration controller iteratively performs concurrently, a write test with the write delay, a read test with the read delay, and a CAC test with the CAC delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until one or more of a read edge, a write edge, and a CAC edge are detected.

Abstract: A calibration controller tests an electronic circuit to identify an initial read check with a read delay, an initial write check with a write delay, and an initial command, address, control (CAC) check with a CAC delay indicated as passing. Responsive to the initial read check, the initial write check, and the initial CAC check indicated as passing, for each setting of the read delay, the write delay, and the CAC delay, the calibration controller iteratively performs concurrently, a write test with the write delay, a read test with the read delay, and a CAC test with the CAC delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay, the read delay, and the CAC delay for each iteration until one or more of a read edge, a write edge, and a CAC edge are detected.

Abstract: An aspect includes providing communication links from a memory controller to contents of a plurality of bit locations in a plurality of memory devices. A failing bit location in the plurality of bit locations is detected by the memory controller. A replacement bit location for the failing bit location is selected and a replacement communication link to the replacement bit location is provided by the memory controller. A request to access contents of the failing bit location received after the selecting and providing the replacement communication link is performed by accessing contents of the replacement bit location via the replacement communication link.

Abstract: Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

Abstract: A method, system and memory controller are provided for implementing signal integrity fail recovery and mainline calibration for Dynamic Random Access Memory (DRAM). After identifying a failed DRAM, the DRAM is marked as bad and taken out of mainline operation. Characterization tests and periodic calibrations are run to evaluate optimal settings and to determine if the marked DRAM is recoverable. If recoverable, the marked DRAM chip is redeployed. If unrecoverable, error reporting is provided to the user.