Abstract: An apparatus and method for signal detection in which a digital sample stream is fed round robin into a plurality of buffers, which are sequentially compared with a reference signal to determine a match. A processor determines the chronological order of the samples in each bit of each buffer, and directs a bitwise comparison between the signal in each buffer with the reference to determine a match, e.g., by correlation. The apparatus and method are preferably implemented with a Field-Programmable Gate Array (FPGA). This scheme permits real time correlation of a data stream with a reference without use of shift registers, or a significant number of dedicated logic blocks.

Abstract: An apparatus provides a correction value for an oscillator. At least one parameter sensor measures a system parameter influencing the oscillator. A lookup table determines a cycle adjustment value based on the system parameter. A processor joined to the oscillator implements the cycle adjustment value to correct for oscillator variation. Cycle adjustment values can be computed in both whole cycles and partial cycles through accumulated error thresholding. The parameter sensor can be a temperature sensor, a voltage sensor or both kinds of sensors. The lookup table and processor can have additional terms to account for hysteresis in the oscillator.