Patents by Inventor JEREMY T. EKMAN

JEREMY T. EKMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063810
    Abstract: Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: Timothy Lindquist, Zachary Kauffman, Jeremy T. Ekman, Scott M. Willenborg
  • Publication number: 20230384978
    Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 30, 2023
    Inventors: Jarrett Betke, George Russell Zettles, IV, Jeremy T Ekman, Austin Carter
  • Patent number: 11762584
    Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jarrett Betke, George Russell Zettles, IV, Jeremy T. Ekman, Austin Carter
  • Patent number: 11675707
    Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: June 13, 2023
    Assignee: International Business Machines Corporation
    Inventors: Daniel Frank Moertl, Damir Anthony Jamsek, Andrew Kenneth Martin, Charalampos Pozidis, Robert Edward Galbraith, Jeremy T. Ekman, Abby Harrison, Gerald Mark Grabowski, Steven Norgaard
  • Publication number: 20220129194
    Abstract: Techniques facilitating write-only device state inferences. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise: a monitor component; and a state component. The monitor component can compare a property of a feedback signal output by a write-only device with a reference signal. The state component can determine a state of the write-only device based on a comparison between the property and the reference signal.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Jarrett Betke, George Russell Zettles, IV, Jeremy T. Ekman, Austin Carter
  • Publication number: 20210216470
    Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Inventors: Daniel Frank Moertl, Damir Anthony Jamsek, Andrew Kenneth Martin, Charalampos Pozidis, Robert Edward Galbraith, Jeremy T. Ekman, Abby Harrison, Gerald Mark Grabowski, Steven Norgaard
  • Patent number: 10990537
    Abstract: A memory system and method for storing data in one or more storage chips includes: one or more memory cards each having a plurality of storage chips, and each chip having a plurality of dies having a plurality of memory cells; a memory controller comprising a translation module, the translation module further comprising: a logical to virtual translation table (LVT) having a plurality of entries, each entry in the LVT configured to map a logical address to a virtual block address (VBA), where the VBA corresponds to a group of the memory cells on the one or more memory cards, wherein each entry in the LVT further includes a write wear level count to track the number of writing operations to the VBA, and a read wear level count to track the number of read operations for the VBA mapped to that LVT entry.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Daniel Frank Moertl, Damir Anthony Jamsek, Andrew Kenneth Martin, Charalampos Pozidis, Robert Edward Galbraith, Jeremy T. Ekman, Abby Harrison, Gerald Mark Grabowski, Steven Norgaard
  • Patent number: 10649031
    Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jeremy T. Ekman, Donald J. Ziebarth, George R. Zettles, IV, Trevor J. Timpane
  • Patent number: 10642673
    Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: May 5, 2020
    Inventors: Donald J. Ziebarth, Jeremy T. Ekman, Trevor J. Timpane, George R. Zettles, IV
  • Publication number: 20190219636
    Abstract: Hardware assisted high speed serial (HSS) transceiver testing including receiving, by a link layer hardware state machine on a HSS transmitting device, an instruction to generate a test pattern, wherein the test pattern comprises a sequence of data units; loading, by the link layer hardware state machine, each unique data unit into embedded random access memory (RAM); generating, by the link layer hardware state machine, the test pattern comprising the sequence of data units using the unique data units stored in the embedded RAM, wherein at least one of the unique data units is repeated in the sequence of data units of the test pattern; and sending, by the link layer hardware state machine, the generated test pattern to an input of a HSS transceiver.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 18, 2019
    Inventors: JEREMY T. EKMAN, DONALD J. ZIEBARTH, GEORGE R. ZETTLES, IV, TREVOR J. TIMPANE
  • Publication number: 20190205194
    Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.
    Type: Application
    Filed: January 2, 2018
    Publication date: July 4, 2019
    Inventors: DONALD J. ZIEBARTH, JEREMY T. EKMAN, TREVOR J. TIMPANE, GEORGE R. ZETTLES, IV