Patents by Inventor Jeroen H. C. J. Stessen

Jeroen H. C. J. Stessen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and device for adding noise to a video signal for improving a display of the video signal
    Patent number: 6724437
    Abstract: In a display driving method, noise is added (NG, AD) to a video signal before the video signal is subjected to a dithering operation (DC). The invention is preferably applied to render non-moving dither patterns invisible in a plasma display panel driving method in which the display signal is subjected to a (Floyd-Steinberg) dithering.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: April 20, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Eric P. Funke, Jeroen H. C. J. Stessen, Age J. Van Dalfsen
  • a METHOD AND DEVICE FOR ADDING NOISE TO A VIDEO SIGNAL FOR IMPROVING A DISPLAY OF THE VIDEO SIGNAL
    Publication number: 20030133045
    Abstract: In a display driving method, noise is added (NG, AD) to a video signal before the video signal is subjected to a dithering operation (DC).
    Type: Application
    Filed: December 22, 1998
    Publication date: July 17, 2003
    Inventors: ERIC P. FUNKE, JEROEN H.C.J. STESSEN, AGE J. VAN DALFSEN
  • Output timebase corrector
    Patent number: 6297849
    Abstract: An output timebase corrector converts orthogonal sampled video (VS) into asynchronous sampled video (VOS) with asynchronous sample values occurring at clock instants (TC) of a clock signal (CLK). The asynchronous sampled video (VOS) is displayed on a display screen of a display device (DD). A discrete time oscillator (DTO) of a time-discrete phase-locked loop (PLL) supplies a time base signal (OS). The time-discrete phase-locked loop (PLL) determines a phase difference (PE) between the time base signal (OS) and reference instants (FB) indicating a timing of a line deflection of the display device (DD) to obtain the time base signal (OS) being locked to the reference instants (FB). The time base signal (OS) controls a sample rate converter (SRC) such that the asynchronous video values (VOS) which occur at the clock instants (TC) are interpolated from the orthogonal sampled video (VS) by the sample rate converter (SRC) such that the video signal is displayed on the correct position on the display screen.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: October 2, 2001
    Assignee: U.S. Philips Corporation
    Inventors: Jeroen H. C. J. Stessen, Antonius H. H. J. Nillesen
  • Time-discrete phase-locked loop
    Patent number: 6100661
    Abstract: A time-discrete phase-locked loop includes a discrete time oscillator (DTO) which supplies a periodical oscillator signal (OS) representing oscillator values (OV) at corresponding clock instants (TC) of a clock signal (CLK). A position-determining circuit (P) generates a time-discrete synchronization instant (SI) representing a position of an analog synchronizing pulse (SP) of a video signal with sub-clock period accuracy. A phase detector (PD) determines a phase error (PE) between the discrete time oscillator signal (OS) and the synchronization instant (SI) by using the synchronization instant (SI), a value (OV1) of the discrete time oscillator signal (OS) at a clock instant (TC1) related to the synchronization instant (SI), and the slope of the oscillator signal (OS). A period of the oscillator signal (OS) depends on the phase error (PE). By using the slope of the oscillator signal (OS), the phase error (PE) is independent of this slope.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 8, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Jeroen H. C. J. Stessen, Age J. Van Dalfsen