Abstract: A host IO devices directly implements host read operations on both local memory, and on peer memory via a PCIe non-transparent bridge. When a host read operation is received by a host IO device from a host, the host IO device uses an API to obtain the physical address of the requested data on the peer memory, and generates a PCIe Transaction Layer Packet (TLP) addressed to the address in the peer memory. The TLP addressed to an address in the peer memory is passed over the NTB to the peer compute node to retrieve the data stored in the addressed slot of peer memory. The requested data is returned to the host IO device over the NTB, stored in a buffer, and read out to the host to directy respond to the host read operation.

Abstract: A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.

Abstract: A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.

Abstract: A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.

Abstract: Storage node blades in a data storage system utilize queue pairs associated with point-to-point links to perform RDMA transactions with memory components associated with other storage node blades. Higher quality of service queue pairs are used for system message transactions and lower quality of service queue pairs are used for remote direct memory access data. Postings to a relatively higher priority queue pair are reduced when a corresponding relatively lower priority queue pair between the same pair of storage nodes via the same switch is starved of bandwidth. Postings to the relatively higher priority queue pair are increased when bandwidth starvation is remediated.

Abstract: A data storage system has first and second computing nodes that are interconnected by a switchless fabric. Each storage node includes first and second paired storage directors with an interconnecting communication link. Atomic operations sent between the computing nodes are mediated by network adapters. Atomic operations sent between paired storage directors via the interconnecting communication link are provided to a network adapter via an internal port and mediated by network adapter. The interconnecting communication links can be used as a backup path for atomic operations in the event of a link failure of the switchless fabric.

Abstract: Described are techniques for processing a request to access global memory. For a first processor included on a first of a plurality of boards connected by a fabric, a logical address is determined for a global memory location in a system global memory. A first physical address for the logical address is determined. It is determined whether the first physical address is included in a first global partition of the first board. If so, first processing is performed including updating a memory map to map a window of the first processor's logical address space to a physical memory segment located within the first global partition. Otherwise, if the first physical address is included in a second of the plurality of global partitions physically located on one of the plurality of boards other than said first board, second processing is performed to issue the request over the fabric.

Abstract: Described are techniques for partitioning memory. A plurality of boards is provided. Each of the plurality of boards includes a physical memory portion and a set of one or more processor. The physical memory portion in each of said plurality of boards is partitioned into a plurality of logical partitions including a global memory partition accessible by any processor on any of the plurality of boards and one or more other memory partitions configured for use by one or more processors of said each board. Each of the one or more other memory partitions not being accessible to a processor on a board other than said each board.