Patents by Inventor Jerome Teysseyre
Jerome Teysseyre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128197Abstract: In a general aspect, an assembly includes a panel of organic substrate core material having a cavity defined therein, a module substrate disposed in the cavity, and a semiconductor die disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material, and a metal layer. The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.Type: ApplicationFiled: October 16, 2023Publication date: April 18, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Olaf ZSCHIESCHANG, Oseob JEON, Jihwan KIM, Roveendra PAUL, Klaus NEUMAIER, Jerome TEYSSEYRE
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Publication number: 20240128140Abstract: In one general aspect, an apparatus can include a semiconductor die, a molding material disposed around at least a portion of the semiconductor die, and a pair of leads electrically coupled to the semiconductor die and aligned along a first direction from the molding material. The molding material can define an elongated protrusion aligned along a second direction orthogonal to the first direction, and a notch disposed between the pair of leads.Type: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Seungwon IM, Jeonghyuk PARK, Keunhyuk LEE, Jerome TEYSSEYRE, Paolo BILARDO
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Publication number: 20240120328Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: ApplicationFiled: December 15, 2023Publication date: April 11, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Inpil YOO, Jooyang EOM
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Patent number: 11935817Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.Type: GrantFiled: October 15, 2020Date of Patent: March 19, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Jerome Teysseyre, Huibin Chen
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Publication number: 20240071860Abstract: In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng LIN, Jerome TEYSSEYRE
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Patent number: 11908826Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.Type: GrantFiled: April 12, 2022Date of Patent: February 20, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Keunhyuk Lee, Jerome Teysseyre, Tiburcio A. Maldo
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Publication number: 20240030122Abstract: A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.Type: ApplicationFiled: July 19, 2022Publication date: January 25, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong LIU, Yusheng LIN, Jerome TEYSSEYRE
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Publication number: 20240030108Abstract: In a general aspect, an electronic device assembly includes a circuit including at least one semiconductor die, and a molded body encapsulating the circuit. The molded body has a primary surface arranged in a plane and a side surface that is non-parallel with the plane. The assembly also includes a slot defined in the primary surface of the molded body, and a signal lead extending out of the side surface of the molded body. The signal lead is electrically coupled with the circuit and has a plurality of bends that include a bend of that is at least partially disposed in the slot.Type: ApplicationFiled: June 30, 2023Publication date: January 25, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Oseob JEON, Chee Hiong CHEW, Seungwon IM
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Patent number: 11848320Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: GrantFiled: August 29, 2022Date of Patent: December 19, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Inpil Yoo, JooYang Eom
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Patent number: 11810775Abstract: A method includes disposing a semiconductor die between a first high voltage isolation carrier and a second high voltage isolation carrier, disposing a first molding material in a space between the semiconductor die and the first high voltage isolation carrier, and disposing a conductive spacer between the semiconductor die and the second high voltage isolation carrier. The method further includes encapsulating the first molding material and the conductive spacer with a second molding material.Type: GrantFiled: July 23, 2021Date of Patent: November 7, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Jerome Teysseyre
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Publication number: 20230326902Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.Type: ApplicationFiled: April 12, 2022Publication date: October 12, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Keunhyuk LEE, Jerome TEYSSEYRE, Tiburcio A. MALDO
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Patent number: 11735508Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: November 4, 2021Date of Patent: August 22, 2023Assignee: SEMICONDUCTOR COMONENTS INDUTRIES, LLCInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
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Publication number: 20230230895Abstract: In one general aspect, an apparatus can include a first module including a first semiconductor die, and a first heatsink coupled to the first module where the first heatsink includes a substrate and a first plurality of protrusions. The apparatus can also include a second module including a second semiconductor die, and a second heatsink coupled to the second module and including a second plurality of protrusions. The apparatus can also include a cover defining a channel where the first plurality of protrusions of the first heatsink and the second plurality of protrusions of the second heatsink are disposed within the channel.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Roveendra PAUL, Dukyong LEE
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Publication number: 20230225044Abstract: In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.Type: ApplicationFiled: January 13, 2023Publication date: July 13, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Oseob JEON, Seungwon IM, Roveendra PAUL, Jerome TEYSSEYRE
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Publication number: 20230207411Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina ESTACIO, Jerome TEYSSEYRE, Elsie Agdon CABAHUG
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Patent number: 11621203Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.Type: GrantFiled: August 13, 2019Date of Patent: April 4, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Cristina Estacio, Jerome Teysseyre, Elsie Agdon Cabahug
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Patent number: 11616006Abstract: According to an aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die coupled to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, where at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.Type: GrantFiled: July 9, 2019Date of Patent: March 28, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Clemens Ypil Quinones, Elsie Agdon Cabahug, Jerome Teysseyre
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Patent number: 11610832Abstract: In one general aspect, an apparatus can include a module including a semiconductor die. The apparatus can include a heatsink coupled to the module and including a substrate, and a plurality of protrusions. The apparatus includes a cover defining a channel where the channel is outside of the module and the plurality of protrusions of the heatsink are disposed within the channel, and a sealing mechanism is disposed between the cover and the module is in contact with the module.Type: GrantFiled: May 14, 2020Date of Patent: March 21, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Roveendra Paul, Dukyong Lee
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Publication number: 20230075519Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Maria Cristina ESTACIO, Seungwon IM
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Publication number: 20230071048Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: STMICROELECTRONICS PTE LTDInventors: Jing-En LUAN, Jerome TEYSSEYRE