Patents by Inventor Jerome Tjia
Jerome Tjia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8615621Abstract: An Accelerated Storage Controller (ASC) in an electronic device allows both conventional (slower) application processor to memory interfaces to be employed transparently to existing software, while also allowing software configuration to realize an accelerated storage architecture on demand. Some use cases for the electronic device do not require accelerated storage, and a bypass mode does not require any modification to existing software. Other use cases (such as fast download of multiple gigabytes of media) benefit from an accelerated storage architecture offloading transfer from the electronic device application processor, but could also work with the traditional processor to memory interface, at the cost of slower downloads. Embodiments of the present invention provide for both these possibilities in a software-configurable architecture. Furthermore, a number of other connectivity options are provided under software control to optimize performance and connectivity for different use case scenarios.Type: GrantFiled: December 23, 2010Date of Patent: December 24, 2013Assignee: ST-Ericsson SAInventors: Han van Holder, Charles Razzell, Lixin Liang, Chee Ee Lee, Jerome Tjia, Marcel van Roosmalen
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Patent number: 8595725Abstract: A collaboration request may be sent to a host or a peripheral when a job is to be processed. The job may include one or more tasks. The host determines which device is better suited to act as host by analyzing the type of task or job to be executed and the capabilities of the host and peripheral. If the peripheral is better suited to act as host, the host and peripheral swap roles and control of a task or job is transferred to the peripheral. The host and peripheral may return to their default roles once the task or job is complete.Type: GrantFiled: May 20, 2005Date of Patent: November 26, 2013Assignee: NXP, B.V.Inventors: Jerome Tjia, Zhenyu Zhang
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Patent number: 8396913Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.Type: GrantFiled: April 11, 2006Date of Patent: March 12, 2013Assignee: NXP B.V.Inventors: Tianyan Pu, Lei Bi, Jerome Tjia
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Patent number: 8269522Abstract: A current boost circuit acts as an “eye opener” for a digital bus line. A controlled current injects a fraction of the normal signaling current magnitude from a source driver onto the bus line, after a transition between the two logical states on the bus line is detected. The duration of the additional current injection is a fraction of the unit interval. In one embodiment, a linear system uses the summation of a proportional boost current and a delayed and negated proportional boost current. In another embodiment, a positive or negative edge detection circuit triggers a monostable pulse generator that controls the injection of short bursts of additional current into the bus lines. In some embodiments the boost current is suppressed when the bus line is driven from a driver other than the source driver.Type: GrantFiled: December 13, 2010Date of Patent: September 18, 2012Assignee: ST-Ericsson SAInventors: Charles Razzell, Hong Sair Lim, Batuhan Okur, Jerome Tjia, Tue Fatt David Wee
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Publication number: 20110221521Abstract: A current boost circuit acts as an “eye opener” for a digital bus line. A controlled current injects a fraction of the normal signaling current magnitude from a source driver onto the bus line, after a transition between the two logical states on the bus line is detected. The duration of the additional current injection is a fraction of the unit interval. In one embodiment, a linear system uses the summation of a proportional boost current and a delayed and negated proportional boost current. In another embodiment, a positive or negative edge detection circuit triggers a monostable pulse generator that controls the injection of short bursts of additional current into the bus lines. In some embodiments the boost current is suppressed when the bus line is driven from a driver other than the source driver.Type: ApplicationFiled: December 13, 2010Publication date: September 15, 2011Inventors: Charles Razzell, Hong Sair Lim, Batuhan Okur, Jerome Tjia, Tue Fatt David Wee
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Publication number: 20110161543Abstract: An Accelerated Storage Controller (ASC) in an electronic device allows both conventional (slower) application processor to memory interfaces to be employed transparently to existing software, while also allowing software configuration to realize an accelerated storage architecture on demand. Some use cases for the electronic device do not require accelerated storage, and a bypass mode does not require any modification to existing software. Other use cases (such as fast download of multiple gigabytes of media) benefit from an accelerated storage architecture offloading transfer from the electronic device application processor, but could also work with the traditional processor to memory interface, at the cost of slower downloads. Embodiments of the present invention provide for both these possibilities in a software-configurable architecture. Furthermore, a number of other connectivity options are provided under software control to optimize performance and connectivity for different use case scenarios.Type: ApplicationFiled: December 23, 2010Publication date: June 30, 2011Applicant: ST-Ericsson SAInventors: Han van Holder, Charles Razzell, Lixin Liang, Chee Ee Lee, Jerome Tjia, Marcel van Roosmalen
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Publication number: 20100011043Abstract: A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.Type: ApplicationFiled: April 11, 2006Publication date: January 14, 2010Applicant: NXP B.V.Inventors: Tianya Pu, Lei Bi, Jerome Tjia
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Patent number: 7640385Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.Type: GrantFiled: May 22, 2003Date of Patent: December 29, 2009Assignee: ST-Ericsson SAInventors: Chee Yu Ng, Yeow Khai Chang, Jerome Tjia, Kawshol Sharma
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Patent number: 7583105Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.Type: GrantFiled: December 29, 2004Date of Patent: September 1, 2009Assignee: NXP B.V.Inventors: Rick Franciscus Jozef Stopel, Jerome Tjia
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Patent number: 7493408Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.Type: GrantFiled: May 19, 2004Date of Patent: February 17, 2009Assignee: NXP, B. V.Inventors: Yeow Khai Chang, Jerome Tjia, Weng Fei Moo
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Patent number: 7484031Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.Type: GrantFiled: May 24, 2005Date of Patent: January 27, 2009Assignee: NXP B.V.Inventor: Jerome Tjia
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Publication number: 20080141259Abstract: A collaboration request may be sent to a host or a peripheral when a job is to be processed. The job may include one or more tasks. The host determines which device is better suited to act as host by analyzing the type of task or job to be executed and the capabilities of the host and peripheral. If the peripheral is better suited to act as host, the host and peripheral swap roles and control of a task or job is transferred to the peripheral. The host and peripheral may return to their default roles once the task or job is complete.Type: ApplicationFiled: May 20, 2005Publication date: June 12, 2008Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Jerome Tjia, Zhenyu Zhang
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Patent number: 7383372Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second station. The protocol comprises a first mode for transferring the requests in a first request format at a first communication speed and at least a second mode for transferring said requests in a second request format at a second speed. The second station is arranged to receive requests in a mode selected from a group of modes comprising said first and second modes, and is arranged to give a first indication to said first station if it is arranged to operate according to the first mode and a second indication if it is arranged to operate according to the second mode. The first station comprises a processor, a controller, and a translator. The processor is operable to generate request properties for requests in the first request format.Type: GrantFiled: May 21, 2003Date of Patent: June 3, 2008Assignee: NXP B.V.Inventors: Jerome Tjia, Bart Vertenten
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Patent number: 7340554Abstract: An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.Type: GrantFiled: May 12, 2004Date of Patent: March 4, 2008Assignee: NXP B.V.Inventors: Chee Ee Lee, Constantin Socol, Jerome Tjia
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Publication number: 20070245059Abstract: A bus connection device, in the form of a hardware dongle, can be connected to a first electronic device, in the form of a USB peripheral device, and a second electronic device can be connected thereto. The dongle can determine whether the second connected device is a USB host device or a USB peripheral device and, if the second electronic device is a USB host device, it is connected directly to the first electronic device. If the second electronic device is a USB peripheral device, the bus connection device operates to allow the first electronic device to operate as a host device. When the bus connection device is operating to allow the first electronic device to act as a USB host device, it regularly sends tokens to the first electronic device and to the second electronic device, to which the first electronic device can respond by transmitting data intended for the second electronic device, and to which the second electronic device can respond by transmitting data intended for the first electronic device.Type: ApplicationFiled: May 24, 2005Publication date: October 18, 2007Inventor: Jerome Tjia
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Publication number: 20070152738Abstract: A pull-up circuit comprises an operational amplifier which forms part of a feedback circuit, acting to bring a pull-up circuit output equal to a reference voltage input. The pull-up circuit may form part of a USB transceiver for incorporation in a USB Device. When the supply voltage of the USB Device is sufficiently high, it is used to provide the required pull-up voltage, with the feedback circuit including the operational amplifier the USB Device is not high enough to provide the required pull-up voltage. In that case, the USB bus voltage is used to generate the reference voltage which is used as an input to the feedback circuit.Type: ApplicationFiled: December 29, 2004Publication date: July 5, 2007Applicant: KONINKLIJKE PHILIPS ELECTRONIC, N.V.Inventors: Rick Stopel, Jerome Tjia
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Publication number: 20070028011Abstract: An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.Type: ApplicationFiled: May 12, 2004Publication date: February 1, 2007Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Chee Lee, Constantin Socol, Jerome Tjia
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Patent number: 7054975Abstract: The present invention relates to a bus system comprising a first and second station (10, 14) coupled via a bus (12) for transferring data and control signals, the bus (12) operating according to a protocol in which the first station (10) repeatedly sends requests (200, 210, 220, 230) for data to the second station, the second station (14) responding to each request (200, 210, 220, 230) by sending a message with a data item or sending a negative acknowledge signal (24), wherein the second station (14) comprises: an interruptable processor (15) for generating data items; a first in first out buffer (160) coupled between the processor (15) and the bus (12), for buffering data items for successive messages in a first in first out order, the processor (15) being programmed to start writing the data items to the buffer (160) in response to an interrupt (204, 234); a bus interface (162) arranged to handle the protocol, sending data items from the buffer (160) in the messages, the bus interface (162) sending an inType: GrantFiled: October 23, 2001Date of Patent: May 30, 2006Assignee: Koninklijke Philips Electronics N.V.Inventor: Jerome Tjia
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Publication number: 20060059289Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.Type: ApplicationFiled: May 22, 2003Publication date: March 16, 2006Inventors: Chee Ng, Yeow Chang, Jerome Tjia, Kawshol Sharma
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Publication number: 20050262262Abstract: A method of transferring bulk and control data from a first device to a second device over a USB bus comprises storing transfer descriptors, each including a transfer descriptor header and payload data, in a buffer memory in the first device. The data is read in packets for transfer to the second device, with packets being read from the transfer descriptors cyclically. When the first and second transfer descriptor headers, in first and second transfer descriptors respectively, define a common endpoint, data packets are read from only the first transfer descriptor, until such time as it is detected that all data packets from the first transfer descriptor have been transmitted, and thereafter data packets are read from the second transfer descriptor.Type: ApplicationFiled: May 19, 2004Publication date: November 24, 2005Inventors: Yeow Chang, Jerome Tjia, Weng Moo