Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: Some embodiments include a transmitter having a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

Abstract: In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.

Abstract: In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Abstract: A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.

Abstract: In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Abstract: In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.

Abstract: A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.

Abstract: Point-to-point AC impedance compensation calculates and matches AC impedance for integrated circuit input and output buffers, taking into consideration impedances of printed circuit boards, connectors, cards, cables, and/or other interfaces on a computer bus, upon computer system power-up or on demand during operation using no additional package pins or traces in the printed circuit board, connector, card, or cable.

Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

Abstract: An apparatus, method and means for providing a clock signal and an inverted clock signal having corresponding rise and fall edge rates, being resistant to load variations, process variations, voltage variations, and temperature variations. The apparatus output exceeds a threshold voltage for apparatus circuit paths. In one aspect of the invention, a combination of N channel and P channel devices, viewed as symmetrical P stacks and N stacks, are utilized. Low output impedance and high gain is provided for resistance to load variations.

Abstract: A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver.

Abstract: An apparatus and method are described for minimizing the time required to perform verify operations in a semiconductor memory having a memory cell capable of being programmed, erased, and repaired, such as a flash EEPROM (electrically erasable programmable read only memory). The apparatus minimizes the time required to verify that the memory cell was correctly programmed, erased, and repaired. The apparatus includes a word a decoder, a driver, and a means for switching voltage levels supplied to the decorder and driver. The driver is comprised of a p-channel transistor having an n-well electrically coupled to a first power line, and a p-substrate. When the memory cell is to be accessed, the driver is activated and drives the word line with a voltage on a second power line. The the second power line is switched from a first voltage level to a second voltage level in order to initiate a verify process while the first power line is maintained at an approximately constant voltage.

Abstract: A data transfer system includes a buffer for storing data to be transferred out of the buffer and a register circuit coupled to the buffer for receiving the data from the buffer. The buffer generates a first indication signal when the buffer is almost empty. The buffer generates a second indication signal when the buffer is empty. The register circuit generates a request signal to receive the data from the buffer. The data transfer system further includes a throttling circuit coupled to the buffer and the register circuit for throttling data transmission to the register circuit from the buffer when the buffer generates the first indication signal and for stopping data transmission to the register circuit from the buffer when the buffer generates the second indication signal. The throttling circuit receives the first and second indication signals and the request signal.