Abstract: A cryogen storage vessel at an installation is filled with liquid cryogen from a liquid cryogen storage tank that has a pressure lower than that of the vessel. After headspaces of the vessel and tank are placed in fluid communication with another via a gas transfer vessel and are pressure-balanced, a pump in a liquid transfer line connected between the tank and the vessel is operated to transfer amounts of liquid cryogen from the tank to the vessel via the liquid transfer line and pump as amounts of gaseous cryogen are transferred, through displacement by the pumped cryogenic liquid, from the vessel to the tank.

Abstract: A cryogenic fluid transfer device comprising a first tank, a second tank, and a fluid transfer circuit, wherein the first tank comprises a cryogenic fluid distribution tank configured to store a cryogenic fluid in a liquid phase in a lower part thereof and in a gaseous phase in an upper part thereof, wherein the second tank comprises a cryogenic receiving tank configured to house the cryogenic fluid in liquid phase in a lower part thereof and in gaseous phase in an upper part thereof, wherein the fluid transfer circuit is configured to connect the first and second tanks, the fluid transfer circuit comprising a first pipe connecting the upper parts of the first and second tanks and comprising at least one valve, and a second pipe connecting the lower part of the first tank to the second tank that comprises a pump that has an inlet connected to the first tank and an outlet connected to the second tank, wherein: the pump and the at least one valve of the first line are configured so as to ensure a fluidic connec

Abstract: A cryogen storage vessel at an installation is filled with liquid cryogen from a liquid cryogen storage tank that has a pressure lower than that of the vessel. After headspaces of the vessel and tank are placed in fluid communication with another via a gas transfer vessel and are pressure-balanced, a pump in a liquid transfer line connected between the tank and the vessel is operated to transfer amounts of liquid cryogen from the tank to the vessel via the liquid transfer line and pump as amounts of gaseous cryogen are transferred, through displacement by the pumped cryogenic liquid, from the vessel to the tank.

Abstract: A cryogen storage vessel at an installation is filled with liquid cryogen from a liquid cryogen storage tank that has a pressure lower than that of the vessel. After headspaces of the vessel and tank are placed in fluid communication with another via a gas transfer vessel and are pressure-balanced, a pump in a liquid transfer line connected between the tank and the vessel is operated to transfer amounts of liquid cryogen from the tank to the vessel via the liquid transfer line and pump as amounts of gaseous cryogen are transferred, through displacement by the pumped cryogenic liquid, from the vessel to the tank. Following filling, the tank is disconnected and then driven to another location to repeat the filling process with a second vessel that is at a different location.

Abstract: A cryogen storage vessel at an installation is filled with liquid cryogen from a liquid cryogen storage tank that has a pressure lower than that of the vessel. After headspaces of the vessel and tank are placed in fluid communication with another via a gas transfer vessel and are pressure-balanced, a pump in a liquid transfer line connected between the tank and the vessel is operated to transfer amounts of liquid cryogen from the tank to the vessel via the liquid transfer line and pump as amounts of gaseous cryogen are transferred, through displacement by the pumped cryogenic liquid, from the vessel to the tank.

Abstract: This invention relates generally to a vapor vent system for an internal combustion engine such as an outboard marine fuel injected engine. The vapor vent system includes a snap assembly decoupled float vapor vent in order to vent vapors from the vapor separator. The snap assembly design reduces costs, vibration and assembly requirements.

Abstract: This invention relates generally to a vapor vent system for an internal combustion engine such as an outboard marine fuel injected engine. The vapor vent system includes a snap assembly decoupled float vapor vent in order to vent vapors from the vapor separator. The snap assembly design reduces costs, vibration and assembly requirements.

Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

Abstract: Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.

Abstract: The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer's orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.

Abstract: A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.

Abstract: A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.

Abstract: A new and improved external corner protector is fabricated from predetermined materials and comprises a vertex portion, and a pair of leg members which diverge outwardly at a predetermined included angle with respect to each other from the vertex portion. The vertex portion and distal end portions of the leg members have relatively enlarged cross-sectional dimensions relative to the cross-sectional dimensions comprising those portions of the leg members which integrally interconnect the distal end portions of the leg members to the vertex portion, wherein the relatively enlarged cross-sectional dimensions serve to reinforce the vertex portion and to dispose only such relatively enlarged distal end portions of the leg members into contact with the external side wall members of the palletized load which define the external corner region being protected.

Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

Abstract: The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer's orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.