Abstract: A bootstrap sample and hold circuit accurately acquires and holds values of a high frequency analog input signal, to avoid harmonic distortion of a signal representing the analog input signal in, for example, a pipeline ADC, includes a first sampling MOSFET coupling the analog input signal to a sampling capacitor. A bootstrap circuit includes a bootstrap capacitor. First and second MOSFETs couple the bootstrap capacitor between a first reference voltage and ground in response to pulses of a first clock signal. Third and fourth MOSFETs then couple the bootstrap capacitor between the gate and source of the sampling MOSFET in response to non-overlapping pulses of a second clock signal to apply a constant gate-to-source voltage to the sampling MOSFET, the gate-to-source voltage having a magnitude equal to the difference between a first reference voltage and ground during the pulses of the second clock signal.

Abstract: Large "inactive" N+ regions are provided in P channel junction field effect transistors (JFETs) or NPN transistors immediately adjacent to "active" areas thereof to getter impurities away from the active areas. The ratio of inactive N+ area to the total area of the transistors is selected to provide suitably low noise measurements at low frequencies. Low noise amplifier circuitry is provided wherein all transistors in the AC signal path include unusually large ratios of inactive N+ area to total transistor area in order to provide greatly reduced low frequency noise levels.

Abstract: A method for manufacturing high speed semiconductor devices by selectively reducing the minority carrier lifetime in regions susceptible to minority carrier charge storage. The selective reduction is achieved by implanting ions of low atomic weight into the surface of the semiconductor crystal in order to locally reduce the sub-surface lifetime.