Patents by Inventor Jerry Liew

Jerry Liew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of fabrication
    Patent number: 11335791
    Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 17, 2022
    Assignee: X-FAB SARAWAK SDN. BHD.
    Inventors: Jerry Liew, Jee Chang Lai
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
    Publication number: 20190355837
    Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 21, 2019
    Applicant: X-FAB Sarawak Sdn. Bhd.
    Inventors: Jerry LIEW, Jee Chang LAI
  • Manufacturing integrated circuit components having multiple gate oxidations
    Patent number: 8546268
    Abstract: STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage) region (GX1), MV (intermediate voltage) region (GX3) and HV (high voltage) region (GX5) respectively followed by a gate poly deposition.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: October 1, 2013
    Assignee: X-FAB Semiconductor Foundries AG
    Inventors: Wilson Entalai, Jerry Liew
  • MANUFACTURING INTEGRATED CIRCUIT COMPONENTS HAVING MULTIPLE GATE OXIDATIONS
    Publication number: 20120034783
    Abstract: STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage) region (GX1), MV (intermediate voltage) region (GX3) and HV (high voltage) region (GX5) respectively followed by a gate poly deposition.
    Type: Application
    Filed: April 30, 2009
    Publication date: February 9, 2012
    Inventors: Wilson Entalai, Jerry Liew