Patents by Inventor Jerry W. Johnson

Jerry W. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220066029
    Abstract: The present disclosure provides a method of measuring discrete locations around a perimeter of a pool, the method comprising positioning a laser measurement device at a reference point; aiming the laser measurement device at a discrete location of interest; determining the geometrical position and location of the discrete location of interest relative to the reference point; and storing the geometrical position and location of the discrete location of interest in a database.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Applicant: Tara Manufacturing, Inc.
    Inventors: Jerry W. Johnson, Matt Nuss, Michael Kranz
  • Patent number: 10082388
    Abstract: A method of measuring the perimeter of a swimming pool has been developed. First, a laser measurement device with a rotary motor is placed on a tripod. Next, the device and tripod are located and leveled the laser measurement in an empty swimming pool and the scan sequence is initiated. The laser measurement device is calibrated and then begins collecting a data measurement of the distance from the side of the swimming pool to the laser measurement device. The laser measurement device is rotated laterally at a defined angle to a new position using the rotary motor and the process of collecting a new data measurement is repeated until the laser measurement device has rotated 360°.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: September 25, 2018
    Assignee: TARA MANUFACTURING, INC.
    Inventors: Jerry W. Johnson, Michael Kranz
  • Patent number: 9603329
    Abstract: Herein provided is a new wheat cultivar designated ‘GA 04570-10E46’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04570-10E46’ (such as cultivars and hybrids related thereto). Also provided are tissue cultures of the new wheat variety ‘GA 04570-10E46’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04570-10E46’ with itself or another wheat variety and plants produced by such methods are also provided.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: March 28, 2017
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
  • Patent number: 9560826
    Abstract: Herein provided is a new wheat cultivar designated ‘GA 041293-11E54’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 041293-11E54’ (such as cultivars and hybrids related thereto). This cultivar is a high grain yielding, medium maturing, good test weight, medium height line that has good resistance to races of leaf rust and stripe rust in Georgia and the Southeast, powdery mildew, Hessian flies, and wheat soil-borne mosaic virus. Also provided are tissue cultures of the new wheat variety ‘GA 041293-11E54’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 041293-11E54’ with itself or another wheat variety and plants produced by such methods are also provided.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: February 7, 2017
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
  • Patent number: 9549523
    Abstract: Herein provided is a new wheat cultivar designated ‘GA 04434-11E44’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04434-11E44’ (such as cultivars and hybrids related thereto). This cultivar is a high grain yielding, medium-late maturing, good test weight, short height line that has good resistance to races of leaf rust and stripe rust in Georgia and the Southeast, powdery mildew, and wheat soil-borne mosaic virus. Also provided are tissue cultures of the new wheat variety ‘GA 04434-11E44’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04434-11E44’ with itself or another wheat variety and plants produced by such methods are also provided.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: January 24, 2017
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
  • Publication number: 20160183490
    Abstract: Herein provided is a new wheat cultivar designated ‘GA 04570-10E46’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04570-10E46’ (such as cultivars and hybrids related thereto). Also provided are tissue cultures of the new wheat variety ‘GA 04570-10E46’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04570-10E46’ with itself or another wheat variety and plants produced by such methods are also provided.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 30, 2016
    Applicant: University of Georgia Research Foundation, Inc.
    Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
  • Publication number: 20150309176
    Abstract: A method of measuring the perimeter of a swimming pool has been developed. First, a laser measurement device with a rotary motor is placed on a tripod. Next, the device and tripod are located and leveled the laser measurement in an empty swimming pool and the scan sequence is initiated. The laser measurement device is calibrated and then begins collecting a data measurement of the distance from the side of the swimming pool to the laser measurement device. The laser measurement device is rotated laterally at a defined angle to a new position using the rotary motor and the process of collecting a new data measurement is repeated until the laser measurement device has rotated 360°.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 29, 2015
    Inventors: Jerry W. Johnson, Michael Kranz
  • Patent number: 8859400
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 8680570
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: March 25, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 8350288
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 8, 2013
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 8343856
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 1, 2013
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Publication number: 20120070967
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 22, 2012
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Publication number: 20120068190
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 22, 2012
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 8067786
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: November 29, 2011
    Assignee: International Rectifier Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Patent number: 7994540
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: August 9, 2011
    Assignee: International Rectifier Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Jr., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
  • Publication number: 20100019248
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Applicant: Nitronex Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Publication number: 20100019850
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 28, 2010
    Applicant: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, JR., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
  • Publication number: 20090267188
    Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.
    Type: Application
    Filed: June 20, 2008
    Publication date: October 29, 2009
    Applicant: Nitronex Corporation
    Inventors: Edwin L. Piner, Jerry W. Johnson, John C. Roberts
  • Patent number: 7566913
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: July 28, 2009
    Assignee: Nitronex Corporation
    Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
  • Publication number: 20080246058
    Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 9, 2008
    Applicant: Nitronex Corporation
    Inventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan