Patents by Inventor Jerry W. Johnson
Jerry W. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220066029Abstract: The present disclosure provides a method of measuring discrete locations around a perimeter of a pool, the method comprising positioning a laser measurement device at a reference point; aiming the laser measurement device at a discrete location of interest; determining the geometrical position and location of the discrete location of interest relative to the reference point; and storing the geometrical position and location of the discrete location of interest in a database.Type: ApplicationFiled: September 2, 2020Publication date: March 3, 2022Applicant: Tara Manufacturing, Inc.Inventors: Jerry W. Johnson, Matt Nuss, Michael Kranz
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Patent number: 10082388Abstract: A method of measuring the perimeter of a swimming pool has been developed. First, a laser measurement device with a rotary motor is placed on a tripod. Next, the device and tripod are located and leveled the laser measurement in an empty swimming pool and the scan sequence is initiated. The laser measurement device is calibrated and then begins collecting a data measurement of the distance from the side of the swimming pool to the laser measurement device. The laser measurement device is rotated laterally at a defined angle to a new position using the rotary motor and the process of collecting a new data measurement is repeated until the laser measurement device has rotated 360°.Type: GrantFiled: April 7, 2015Date of Patent: September 25, 2018Assignee: TARA MANUFACTURING, INC.Inventors: Jerry W. Johnson, Michael Kranz
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Patent number: 9603329Abstract: Herein provided is a new wheat cultivar designated ‘GA 04570-10E46’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04570-10E46’ (such as cultivars and hybrids related thereto). Also provided are tissue cultures of the new wheat variety ‘GA 04570-10E46’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04570-10E46’ with itself or another wheat variety and plants produced by such methods are also provided.Type: GrantFiled: December 15, 2015Date of Patent: March 28, 2017Assignee: University of Georgia Research Foundation, Inc.Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
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Patent number: 9560826Abstract: Herein provided is a new wheat cultivar designated ‘GA 041293-11E54’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 041293-11E54’ (such as cultivars and hybrids related thereto). This cultivar is a high grain yielding, medium maturing, good test weight, medium height line that has good resistance to races of leaf rust and stripe rust in Georgia and the Southeast, powdery mildew, Hessian flies, and wheat soil-borne mosaic virus. Also provided are tissue cultures of the new wheat variety ‘GA 041293-11E54’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 041293-11E54’ with itself or another wheat variety and plants produced by such methods are also provided.Type: GrantFiled: October 5, 2015Date of Patent: February 7, 2017Assignee: University of Georgia Research Foundation, Inc.Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
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Patent number: 9549523Abstract: Herein provided is a new wheat cultivar designated ‘GA 04434-11E44’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04434-11E44’ (such as cultivars and hybrids related thereto). This cultivar is a high grain yielding, medium-late maturing, good test weight, short height line that has good resistance to races of leaf rust and stripe rust in Georgia and the Southeast, powdery mildew, and wheat soil-borne mosaic virus. Also provided are tissue cultures of the new wheat variety ‘GA 04434-11E44’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04434-11E44’ with itself or another wheat variety and plants produced by such methods are also provided.Type: GrantFiled: October 5, 2015Date of Patent: January 24, 2017Assignee: University of Georgia Research Foundation, Inc.Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
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Publication number: 20160183490Abstract: Herein provided is a new wheat cultivar designated ‘GA 04570-10E46’ as well as the seeds, plants and derivatives of the new wheat variety ‘GA 04570-10E46’ (such as cultivars and hybrids related thereto). Also provided are tissue cultures of the new wheat variety ‘GA 04570-10E46’ and the plants regenerated therefrom. Methods for producing wheat plants by crossing the new wheat variety ‘GA 04570-10E46’ with itself or another wheat variety and plants produced by such methods are also provided.Type: ApplicationFiled: December 15, 2015Publication date: June 30, 2016Applicant: University of Georgia Research Foundation, Inc.Inventors: Jerry W. Johnson, G. David Buntin, James W. Buck
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Publication number: 20150309176Abstract: A method of measuring the perimeter of a swimming pool has been developed. First, a laser measurement device with a rotary motor is placed on a tripod. Next, the device and tripod are located and leveled the laser measurement in an empty swimming pool and the scan sequence is initiated. The laser measurement device is calibrated and then begins collecting a data measurement of the distance from the side of the swimming pool to the laser measurement device. The laser measurement device is rotated laterally at a defined angle to a new position using the rotary motor and the process of collecting a new data measurement is repeated until the laser measurement device has rotated 360°.Type: ApplicationFiled: April 7, 2015Publication date: October 29, 2015Inventors: Jerry W. Johnson, Michael Kranz
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Patent number: 8859400Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: December 28, 2012Date of Patent: October 14, 2014Assignee: International Rectifier CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Patent number: 8680570Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: January 4, 2013Date of Patent: March 25, 2014Assignee: International Rectifier CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Patent number: 8350288Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: November 22, 2011Date of Patent: January 8, 2013Assignee: International Rectifier CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Patent number: 8343856Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: November 22, 2011Date of Patent: January 1, 2013Assignee: International Rectifier CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Publication number: 20120070967Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: ApplicationFiled: November 22, 2011Publication date: March 22, 2012Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Publication number: 20120068190Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., PET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: ApplicationFiled: November 22, 2011Publication date: March 22, 2012Inventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Patent number: 8067786Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: July 24, 2009Date of Patent: November 29, 2011Assignee: International Rectifier CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Patent number: 7994540Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.Type: GrantFiled: July 24, 2009Date of Patent: August 9, 2011Assignee: International Rectifier CorporationInventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Jr., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
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Publication number: 20100019248Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: ApplicationFiled: July 24, 2009Publication date: January 28, 2010Applicant: Nitronex CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Publication number: 20100019850Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.Type: ApplicationFiled: July 24, 2009Publication date: January 28, 2010Applicant: Nitronex CorporationInventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, JR., Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan
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Publication number: 20090267188Abstract: Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.Type: ApplicationFiled: June 20, 2008Publication date: October 29, 2009Applicant: Nitronex CorporationInventors: Edwin L. Piner, Jerry W. Johnson, John C. Roberts
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Patent number: 7566913Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.Type: GrantFiled: December 4, 2006Date of Patent: July 28, 2009Assignee: Nitronex CorporationInventors: Robert J. Therrien, Jerry W. Johnson, Allen W. Hanson
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Publication number: 20080246058Abstract: Gallium nitride material transistors and methods associated with the same are provided. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. The transistors may be designed to achieve low ACPR values (a measure of excellent linearity), while still operating at high drain efficiencies and/or high output powers. Such properties enable the transistors to be used in RF power applications including third generation (3G) power applications based on W-CDMA modulation.Type: ApplicationFiled: March 31, 2008Publication date: October 9, 2008Applicant: Nitronex CorporationInventors: Walter H. Nagy, Ricardo M. Borges, Jeffrey D. Brown, Apurva D. Chaudhari, James W. Cook, Allen W. Hanson, Jerry W. Johnson, Kevin J. Linthicum, Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Sameer Singhal, Robert J. Therrien, Andrei Vescan