Abstract: A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed.

Abstract: Apparatus and a method for testing the dielectric integrity of an insulated conductor wherein the conductor is immersed in a flowable mass of metal beads and a voltage potential is established between the conductor and the mass of beads to sense any current flow therebetween.

Abstract: A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed.

Abstract: A frequency response equalizer includes a parallel combination of a low-pass integrating circuit and a high-pass differentiating circuit. Both circuits receive an input signal from a reproduce head followed by a preamplifier. Each circuit provides a 90.degree. phase shift with respect to the input signal, equal in magnitude and opposite in sense. A subtraction circuit coupled to the respective outputs of both the integrating and differentiating circuit provides a difference signal of the respective output signals of both circuits. The resulting difference signal represents an amplitude and phase equalized signal.

Abstract: A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed.