Abstract: The present invention relates to a brake controller for a towed vehicle braking system, including a housing or a loom, including an input connector for electrical connection to a towing vehicle and an output connector for electrical connection to a towed vehicle.

Abstract: A head assembly for a crash test dummy includes a skull, a head skin disposed over the skull, and a facial insert disposed between the skull and the head skin and having a plurality of defined cell structures to achieve a biomechanical response that provides for evaluation of potential head injuries during vehicle crash testing.

Abstract: An apparatus may include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus to at least apply at least one orthogonal cover code to at least a first antenna port and a second antenna port. The at least one memory and the computer program code can be further configured to, with the at least one processor, cause the apparatus to at least perform at least one rotation operation associated with at least one signal of the first antenna and the second antenna. The apparatus is caused to at least perform at least one channel estimation based upon the at least one signal of the first antenna and the second antenna.

Abstract: A convenient and quick-release textile, a quick-release slide fastener being provided on the textile includes: a tooth easy-release region being provided on the teeth of the quick-release slide fastener. A pulling member is provided beside the tooth easy-release region. Quick positioners having a mutual positioning function are further provided on both the textile and the pulling member correspondingly. The quick positioner provided on the textile and the quick positioner provided on the pulling member are located on a same side of the quick-release slide fastener, or separately on two sides of the quick-release slide fastener. In this way, the pulling member textile is held easily and covers the tooth easy-release region, thus preventing the tooth easy-release region from separating due to the impact of the unnecessary external force.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A neck assembly for an anthropomorphic test device (ATD) includes a plurality of vertebra discs, a plurality of ligament joints each having a joint element disposed between the vertebra discs, and a torsion assembly coupled to one of the vertebra discs to allow rotation about an axis of the one of the vertebra discs to simulate torsion response of a human neck.

Abstract: A neck assembly for an anthropomorphic test device (ATD) includes a plurality of vertebra discs, a plurality of ligament joints each having a joint element disposed between the vertebra discs, and a torsion assembly coupled to one of the vertebra discs to allow rotation about an axis of the one of the vertebra discs to simulate torsion response of a human neck.

Abstract: A neck assembly for an anthropomorphic test device (ATD) includes a plurality of vertebra discs, a plurality of ligament joints each having a joint element disposed between the vertebra discs, and a torsion assembly coupled to one of the vertebra discs to allow rotation about an axis of the one of the vertebra discs to simulate torsion response of a human neck.

Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Abstract: A head assembly for a crash test dummy includes a skull, a head skin disposed over the skull, and a facial insert disposed between the skull and the head skin and having a plurality of defined cell structures to achieve a biomechanical response that provides for evaluation of potential head injuries during vehicle crash testing.

Abstract: A neck assembly for an anthropomorphic test device (ATD) includes a plurality of vertebra discs, a plurality of ligament joints each having a joint element disposed between the vertebra discs, and a torsion assembly coupled to one of the vertebra discs to allow rotation about an axis of the one of the vertebra discs to simulate torsion response of a human neck.

Abstract: An omnidirectional neck assembly for a crash test dummy includes a plurality of vertebra discs, a plurality of ligament joints each having a joint element disposed between the vertebra discs, the vertebra discs having a profile that can simulate angles of a human neck in all directions.

Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Abstract: A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Abstract: Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.