Abstract: A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.

Abstract: A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Abstract: A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD?60 nm by using a top electrode (TE) hard mask having a thickness?100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD?60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at ?70 nm.

Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

Abstract: An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.

Abstract: A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A metal hard mask layer is provided on the MTJ stack. A stack of multiple dielectric hard masks is formed on the metal hard mask wherein each successive dielectric hard mask has etch selectivity with respect to its underlying and overlying layers. The dielectric hard mask layers are etched in turn selectively with respect to their underlying and overlying layers wherein each successive pattern size is smaller than the preceding pattern size. The MTJ stack is etched selectively with respect to the bottommost combination dielectric and metal hard mask pattern to form a MTJ device having a MTJ pattern size smaller than a bottommost pattern size.

Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A hard mask layer is provided on the MTJ stack. The hard mask layer is patterned to form a hard mask. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on sidewalls of the MTJ device. The sidewall damage is removed by applying a CMP slurry which physically attacks and removes the sidewall damage on the MTJ device.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers on a bottom electrode on a wafer is provided. A hard mask layer is provided on the MTJ stack. The hard mask layer is patterned to form a hard mask. The MTJ stack is patterned to form a MTJ device wherein sidewall damage is formed on sidewalls of the MTJ device. The sidewall damage is removed by applying a CMP slurry which physically attacks and removes the sidewall damage on the MTJ device.

Abstract: A process flow for forming a magnetic tunnel junction (MTJ) cell that is self-aligned to an underlying bottom electrode (BE) is disclosed. The BE is comprised of a lower BE layer having a first width (w1), and an upper (second) BE layer with a second width (w2) where w2>w1. Preferably, the BE has a T shape. A stack of MTJ layers including an uppermost hard mask is deposited on the BE and has width w2 because of a self-aligned deposition process. A dummy MTJ stack is also formed around the first BE layer. An ion beam etch where ions are at an incident angle <90° with respect to the substrate is used to remove extraneous material on the sidewall. Thereafter, an encapsulation layer is deposited to insulate the MTJ cell, and to fill a gap between the first BE layer and dummy MTJ stack.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A bottom electrode layer is provided on a substrate. A seed layer is deposited on the bottom electrode layer. The seed layer and bottom electrode layer are patterned. A dielectric layer is deposited over the patterned seed layer and bottom electrode layer and planarized wherein the seed layer is exposed. Thereafter, a stack of MTJ layers is deposited on the patterned seed layer comprising a pinned layer, a tunnel barrier layer, and a free layer. The MTJ stack is then patterned to form a MTJ device. Because the seed layer was patterned before the MTJ patterning step, the exposure of the device to etching plasma gases is shortened and thus, etch damage is minimized.

Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. An electrode layer is deposited on a stack of MTJ layers on a bottom electrode. A photoresist mask is formed on the electrode layer. The electrode layer is etched away where it is not covered by the photoresist mask to form a metal hard mask. The metal hard mask is passivated during or after etching to form a smooth hard mask profile. Thereafter, the photoresist mask is removed and the MTJ structure is etched using the metal hard mask wherein the metal hard mask remaining acts as a top electrode. The resulting MTJ device has smooth sidewalls and uniform device shape.

Abstract: A KrF (248 nm) photoresist patterning process flow is disclosed wherein photoresist patterns having a sub-100 nm CD are formed on a dielectric antireflective coating (DARC) thereby lowering cost of ownership by replacing a more expensive ArF (193 nm) photoresist patterning process. A key feature is treatment of a DARC such as SiON with a photoresist developer solution that is 0.263 N tetramethylammonium hydroxide (TMAH) prior to treatment with hexamethyldisilazane (HMDS) in order to significantly improve adhesion of features with CD down to about 60 nm. After the HMDS treatment, a photoresist layer is coated on the DARC, patternwise exposed, and treated with the photoresist developer solution to form a pattern therein. Features that were previously resolved by KrF patterning processes but subsequently collapsed because of poor adhesion, now remain upright and intact during a subsequent etch process used to transfer the sub-100 nm features into a substrate.

Abstract: A KrF (248 nm) photoresist patterning process flow is disclosed wherein photoresist patterns having a sub-100 nm CD are formed on a dielectric antireflective coating (DARC) thereby lowering cost of ownership by replacing a more expensive ArF (193 nm) photoresist patterning process. A key feature is treatment of a DARC such as SiON with a photoresist developer solution that is 0.263 N tetramethylammonium hydroxide (TMAH) prior to treatment with hexamethyldisilazane (HMDS) in order to significantly improve adhesion of features with CD down to about 60 nm. After the HMDS treatment, a photoresist layer is coated on the DARC, patternwise exposed, and treated with the photoresist developer solution to form a pattern therein. Features that were previously resolved by KrF patterning processes but subsequently collapsed because of poor adhesion, now remain upright and intact during a subsequent etch process used to transfer the sub-100 nm features into a substrate.

Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. An electrode layer is deposited on a stack of MTJ layers on a bottom electrode. A photoresist mask is formed on the electrode layer. The electrode layer is etched away where it is not covered by the photoresist mask to form a metal hard mask. The metal hard mask is passivated during or after etching to form a smooth hard mask profile. Thereafter, the photoresist mask is removed and the MTJ structure is etched using the metal hard mask wherein the metal hard mask remaining acts as a top electrode. The resulting MTJ device has smooth sidewalls and uniform device shape.

Abstract: Some embodiments include a method of preparing a flexible substrate assembly. Other embodiments of related methods and structures are also disclosed.

Abstract: In some embodiments, a method of manufacturing electronic devices including providing a carrier substrate having a first side, a second side, and a first adhesive at the first side; providing a first flexible substrate; and bonding the first flexible substrate to the first side of the carrier substrate. The first adhesive bonds the first flexible substrate to the first side of the carrier substrate. The carrier substrate comprises a mechanism configured to compensate for a deformation of the carrier substrate. Other embodiments are disclosed.