Patents by Inventor Jesse LAKEMEIER

Jesse LAKEMEIER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for configuring a tester equipped for testing a control unit
    Patent number: 10444745
    Abstract: A method for automated configuration of a tester equipped for testing a control unit. A first and second model of technical systems being executed in the tester. The execution of the models taking place periodically with defined sampling rates. An FPGA executes the first and/or the second model and a CPU executes the first or the second model. A first individual sampling rate is allocated for the first model and a second individual sampling rate is allocated for the second model. The first model is assigned for execution on either the CPU or the FPGA and the second model is assigned for execution on either the CPU or the FPGA. The tester is automatically configured for execution of the first model with the first allocated sampling rate on the FPGA or the CPU and of the second model with the second allocated sampling rate on the FPGA or the CPU.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 15, 2019
    Assignee: dSPACE digital signal processing and control engineering Gmbh
    Inventors: László Juhász, Jesse Lakemeier
  • METHOD FOR CONFIGURING A TESTER EQUIPPED FOR TESTING A CONTROL UNIT
    Publication number: 20170212509
    Abstract: A method for automated configuration of a tester equipped for testing a control unit. A first and second model of technical systems being executed in the tester. The execution of the models taking place periodically with defined sampling rates. An FPGA executes the first and/or the second model and a CPU executes the first or the second model. A first individual sampling rate is allocated for the first model and a second individual sampling rate is allocated for the second model. The first model is assigned for execution on either the CPU or the FPGA and the second model is assigned for execution on either the CPU or the FPGA. The tester is automatically configured for execution of the first model with the first allocated sampling rate on the FPGA or the CPU and of the second model with the second allocated sampling rate on the FPGA or the CPU.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 27, 2017
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: László JUHÁSZ, Jesse LAKEMEIER