Patents by Inventor Jesse Pan
Jesse Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9009445Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.Type: GrantFiled: October 20, 2011Date of Patent: April 14, 2015Assignee: Apple Inc.Inventor: Jesse Pan
-
Publication number: 20130103923Abstract: A system and method for efficiently handling translation look-aside buffer (TLB) misses. A memory management unit (MMU) detects when a given virtual address misses in each available translation-lookaside-buffer (TLB). The MMU determines whether a memory access operation associated with the given virtual address is the oldest, uncompleted memory access operation in a scheduler. If this is the case, a demand table walk (TW) request may be stored in an available entry in a TW queue. During this time, the utilization of the memory subsystem resources may be low. While a demand TW request is stored in the TW queue, subsequent speculative TW requests may be stored in the TW queue. When the TW queue does not store a demand TW request, no more entries of the TW queue may be allocated to store TW requests.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Inventor: Jesse Pan
-
Patent number: 8341379Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.Type: GrantFiled: May 5, 2010Date of Patent: December 25, 2012Assignee: Apple Inc.Inventors: Jesse Pan, Ramesh Gunna
-
Patent number: 8255670Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.Type: GrantFiled: November 17, 2009Date of Patent: August 28, 2012Assignee: Apple Inc.Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
-
Publication number: 20100217951Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.Type: ApplicationFiled: May 5, 2010Publication date: August 26, 2010Inventors: Jesse Pan, Ramesh Gunna
-
Patent number: 7739476Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.Type: GrantFiled: November 4, 2005Date of Patent: June 15, 2010Assignee: Apple Inc.Inventors: Jesse Pan, Ramesh Gunna
-
Publication number: 20100064120Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.Type: ApplicationFiled: November 17, 2009Publication date: March 11, 2010Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
-
Patent number: 7647518Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.Type: GrantFiled: October 10, 2006Date of Patent: January 12, 2010Assignee: Apple Inc.Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
-
Publication number: 20080086622Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicant: P.A. Semi, Inc.Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
-
Publication number: 20070106874Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.Type: ApplicationFiled: November 4, 2005Publication date: May 10, 2007Applicant: P.A. Semi, Inc.Inventors: Jesse Pan, Ramesh Gunna
-
Patent number: 6925584Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.Type: GrantFiled: April 30, 2003Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat
-
Publication number: 20030196146Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.Type: ApplicationFiled: April 30, 2003Publication date: October 16, 2003Applicant: Intel CorporationInventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat
-
Patent number: 6571359Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.Type: GrantFiled: December 13, 1999Date of Patent: May 27, 2003Assignee: Intel CorporationInventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat
-
Patent number: 6539469Abstract: A processor comprises an instruction cache that stores a cache line of instructions and an execution engine for executing the instructions, along with a buffer to store a plurality of entries. A first logic circuit divides the cache line into instruction bundles, each of which gets written into an entry of the buffer. A second logic circuit reads out a number of consecutive instruction bundles from the buffer for dispersal to the execution engine to optimize speculative fetching and maximizing instruction supply to the execution resources of the processor.Type: GrantFiled: October 12, 1999Date of Patent: March 25, 2003Assignee: Intel CorporationInventor: Jesse Pan