Patents by Inventor Jhy-Jyi Sze
Jhy-Jyi Sze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11309348Abstract: The present disclosure relates to a CMOS image sensor having a doped isolation structure separating a photodiode and a pixel device, and an associated method of formation. In some embodiments, the CMOS image sensor has a doped isolation structure separating a photodiode and a pixel device. The photodiode is arranged within the substrate away from a front-side of the substrate. A pixel device is disposed at the front-side of the substrate overlying the photodiode and is separated from the photodiode by the doped isolation structure. Comparing to previous image sensor designs, where an upper portion of the photodiode is commonly arranged at a top surface of a front-side of the substrate, now the photodiode is arranged away from the top surface and leaves more room for pixel devices. Thus, a larger pixel device can be arranged in the sensing pixel, and short channel effect and noise level can be improved.Type: GrantFiled: September 11, 2019Date of Patent: April 19, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Jhy-Jyi Sze, Yimin Huang
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Publication number: 20220102410Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.Type: ApplicationFiled: February 17, 2021Publication date: March 31, 2022Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
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Patent number: 11264525Abstract: A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.Type: GrantFiled: May 21, 2020Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tzu-Jui Wang, Jhy-Jyi Sze, Yuichiro Yamashita, Kuo-Chin Huang
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Publication number: 20220059583Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.Type: ApplicationFiled: November 5, 2021Publication date: February 24, 2022Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
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Patent number: 11227889Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.Type: GrantFiled: November 5, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
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Patent number: 11211419Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.Type: GrantFiled: July 25, 2019Date of Patent: December 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
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Publication number: 20210375959Abstract: A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.Type: ApplicationFiled: April 12, 2021Publication date: December 2, 2021Inventors: Jyh-Ming HUNG, Tzu-Jui WANG, Kuan-Chieh HUANG, Jhy-Jyi SZE
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Publication number: 20210366956Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Inventors: Wei Chuang Wu, Dun-Nian Yaung, Feng-Chi Hung, Jen-Cheng Liu, Jhy-Jyi Sze, Keng-Yu Chou, Yen-Ting Chiang, Ming-Hsien Yang, Chun-Yuan Chen
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Publication number: 20210351218Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.Type: ApplicationFiled: July 20, 2021Publication date: November 11, 2021Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
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Patent number: 11158662Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has an image sensor within a substrate. A first dielectric has an upper surface that extends over a first side of the substrate and over one or more trenches within the first side of the substrate. The one or more trenches laterally surround the image sensor. An internal reflection structure arranged over the upper surface of the first dielectric. The internal reflection structure is configured to reflect radiation exiting from the substrate back into the substrate.Type: GrantFiled: November 26, 2019Date of Patent: October 26, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Yu Chou, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang, Jhy-Jyi Sze
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Publication number: 20210320139Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Jhy-Jyi Sze, Dun-Nian Yaung, Alexander Kalnitsky
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Publication number: 20210313383Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.Type: ApplicationFiled: June 17, 2021Publication date: October 7, 2021Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Yimin Huang
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Patent number: 11139367Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure disposed over a substrate. A plurality of conductive interconnect layers are disposed within the dielectric structure. The plurality of conductive interconnect layers include alternating layers of interconnect wires and interconnect vias. A metal-insulating-metal (MIM) capacitor is arranged within the dielectric structure. The MIM capacitor has a lower conductive electrode separated from an upper conductive electrode by a capacitor dielectric structure. The MIM capacitor vertically extends past two or more of the plurality of conductive interconnect layers.Type: GrantFiled: March 27, 2019Date of Patent: October 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Jung-I Lin, Jhy-Jyi Sze, Alexander Kalnitsky, Yimin Huang, King Liao, Shen-Hui Hong
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Publication number: 20210280620Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.Type: ApplicationFiled: May 5, 2021Publication date: September 9, 2021Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
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Publication number: 20210265412Abstract: The present disclosure, in some embodiments, relates to an image sensing integrated chip. The image sensing integrated chip includes a semiconductor substrate having sidewalls defining one or more trenches on opposing sides of a region of the semiconductor substrate. One or more dielectrics are disposed within the one or more trenches. The semiconductor substrate has a plurality of flat surfaces arranged between the one or more trenches. Adjacent ones of the plurality of flat surfaces define a plurality of triangular shaped protrusions and alternative ones of the plurality of flat surfaces are substantially parallel to one another, as viewed along a cross-sectional view.Type: ApplicationFiled: April 21, 2021Publication date: August 26, 2021Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang
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Publication number: 20210265414Abstract: A BSI image sensor includes a substrate including a front side and a back side opposite to the front side, a pixel sensor disposed in the substrate, and a color filter disposed over the pixel sensor. The pixel sensor includes a plurality of first micro structures disposed over the back side of the substrate. The color filter includes a plurality of second micro structures disposed over the back side of the substrate. The first micro structures are arranged symmetrically to a first axial, and the second micro structures are arranged symmetrically to a second axial.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: WEI-CHIEH CHIANG, KENG-YU CHOU, CHUN-HAO CHUANG, WEN-HAU WU, JHY-JYI SZE, CHIEN-HSIEN TSENG, KAZUAKI HASHIMOTO
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Patent number: 11088196Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.Type: GrantFiled: November 15, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Yimin Huang
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Patent number: 11075242Abstract: The present disclosure relates to a semiconductor device having a lateral resonance structure to coherently reflect light toward the image sensor. The semiconductor device includes an image sensing element arranged within a substrate. A radiation absorption region is arranged within the substrate and above the image sensor, and contains an array of protrusions having a characteristic dimension and an outer border. A resonant structure containing a plurality of deep trench isolation (DTI) structures is disposed on opposing sides of the image sensing element. The (DTI) structures surround the outer border of the array of protrusions. An inner surface of the DTI structure is laterally spaced apart from the outer border of the array of protrusions by a reflective length based on the characteristic dimension of the array of protrusions, thus affecting coherent reflection of light back toward the image sensor.Type: GrantFiled: April 25, 2018Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
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Publication number: 20210217796Abstract: A method of forming an image sensor includes forming a first image sensor element within a substrate. The first image sensor element and the substrate respectively comprise a first material. A second image sensor element is formed within the substrate. Forming the second image sensor element includes forming an isolation layer over the first image sensor element. Further, a buffer layer is formed over the isolation layer and an active layer is formed over the buffer layer. The active layer comprises a second material different from the first material.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventor: Jhy-Jyi Sze
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Patent number: 11063081Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.Type: GrantFiled: May 3, 2019Date of Patent: July 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhy-Jyi Sze, Dun-Nian Yaung, Alexander Kalnitsky