Patents by Inventor Ji-Fu Kung

Ji-Fu Kung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955309
    Abstract: An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zheng-Yang Li, Chian-Chen Kuo, Yi-Cheng Lu, Ji-Fu Kung
  • Patent number: 11916075
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: February 27, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 11609836
    Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: March 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Pei Lin, Ji-Fu Kung, Te-Hsuan Chen, Yi-Lin Hung
  • Publication number: 20220398410
    Abstract: A manufacturing data analyzing method and a manufacturing data analyzing device are provided. The manufacturing data analyzing method includes the following steps. Each of at least one numerical data, at least one image data and at least one text data is transformed into a vector. The vectors are gathered to obtain a combined vector. The combined vector is inputted into an inference model to obtain a defect cause and a modify suggestion.
    Type: Application
    Filed: June 10, 2021
    Publication date: December 15, 2022
    Inventors: Ching-Pei LIN, Ming-Tsung YEH, Chuan-Guei WANG, Ji-Fu KUNG
  • Publication number: 20220384139
    Abstract: An automatic adjustment method and an automatic adjustment device of a beam of a semiconductor apparatus, and a training method of a parameter adjustment model are provided. The automatic adjustment method of the beam of the semiconductor apparatus includes the following steps. The semiconductor apparatus generates the beam. A wave curve of the beam is obtained. The wave curve is segmented into several sections. The slope of each of the sections is obtained. Several environmental factors of the semiconductor apparatus are obtained. According to the slopes and the environmental factors, at least one parameter adjustment command of the semiconductor apparatus is analyzed through the parameter adjustment model.
    Type: Application
    Filed: July 7, 2021
    Publication date: December 1, 2022
    Inventors: Zheng-Yang LI, Chian-Chen KUO, Yi-Cheng LU, Ji-Fu KUNG
  • Publication number: 20220283217
    Abstract: An equipment sensing circuit board and an operation method thereof are provided. The equipment sensing circuit board equipped on a semiconductor equipment includes a main sensor, a backup sensor, a first electronic fuse, a second electronic fuse, and a multiplexer. The main sensor and the backup sensor are used to monitor the operation of the semiconductor equipment to output a main sensing signal and a backup sensing signal respectively. The first electronic fuse is disposed on the main sensor to output a first status signal. The second electronic fuse is disposed on the backup sensor to output a second status signal. The multiplexer is connected to the main sensor, the backup sensor, the first electronic fuse and the second electronic fuse. The multiplexer selects to output the main sensing signal or the backup sensing signal according to the combination of the first state signal and the second state signal.
    Type: Application
    Filed: April 9, 2021
    Publication date: September 8, 2022
    Inventors: Ji-Fu KUNG, Yi-Lin HUNG, Chih-Chung KUO, Wei-Che LIN
  • Publication number: 20220271035
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: May 10, 2022
    Publication date: August 25, 2022
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 11417654
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 16, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Publication number: 20220222162
    Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 14, 2022
    Inventors: Ching-Pei LIN, Ji-Fu KUNG, Te-Hsuan CHEN, Yi-Lin HUNG
  • Patent number: 11119625
    Abstract: A remote control device for a manufacturing equipment and a method for detecting manual control are provided. The method for detecting the manual control on the manufacturing equipment includes the following steps. A cursor pattern is created. When the user interface is automatically controlled, a history location of the cursor pattern shown on a user interface of the manufacturing equipment is detected to obtain a location distribution. The location distribution is stored. A current location of the cursor pattern shown on the user interface is detected. If the current location is not within the location distribution, it is deemed that the user interface is manually controlled.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zheng-Yang Li, Chung-Jung Chen, Chun-Man Li, Li-Hsin Yang, Ching-Pei Lin, Ji-Fu Kung
  • Publication number: 20200381431
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10784261
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Publication number: 20200098755
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10570507
    Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 25, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
  • Patent number: 10529715
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Publication number: 20190276930
    Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.
    Type: Application
    Filed: April 10, 2018
    Publication date: September 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
  • Publication number: 20180204838
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: February 8, 2017
    Publication date: July 19, 2018
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 9958494
    Abstract: For improving wafer fabrication, yield and lifetime of wafers are predicted by determining coefficients of a yield domain for wafer yield prediction and a lifetime domain for a wafer lifetime prediction, an integral domain, an electric/layout domain, a metrology/defect domain, and a machine sensor domain in a hierarchical manner. With the aid of the hierarchically-determined coefficients, noises in prediction can be reduced so that precision of prediction results of the yields or the lifetimes of wafers can be raised.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung
  • Patent number: 9443970
    Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hsin-Ming Hou, Yu-Cheng Tung, Ji-Fu Kung, Wai-Yi Lien, Ming-Tsung Chen
  • Patent number: 9299624
    Abstract: A stacked semiconductor structure and a manufacturing method for the same are provided. The stacked semiconductor structure is provided, which comprises a first semiconductor substrate, a second semiconductor substrate, a dielectric layer, a trench, a via, and a conductive structure. The first semiconductor substrate comprises a first substrate portion and a first conductive layer on an active surface of the first substrate portion. The second semiconductor substrate comprises a second substrate portion and a second conductive layer on an active surface of the second substrate portion. The trench passes through the second substrate portion and exposing the second conductive layer. The via passes through the dielectric layer and exposes the first conductive layer. The conductive structure has an upper portion filling the trench and a lower portion filling the via. Opposing side surfaces of the upper portion are beyond opposing side surfaces of the lower portion.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung