Patents by Inventor Ji-Soo Jang

Ji-Soo Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8126087
    Abstract: A DC offset correction circuit includes a DC offset detector generating a detection voltage based on a result of a comparison of a first reference voltage and a voltage difference between signals input to the DC offset detector, a comparator comparing a second reference voltage and the detection voltage and a third reference voltage and the detection voltage and outputting first and second comparison signals, respectively, as a result of the comparisons, and an up/down counter performing an up or a down count operation in response to one of the first or second comparison signals and, as a result of the up or down count operation, outputting a signal that causes at least one control signal for canceling a DC offset in a signal input to a receiver to be generated.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju Young Han, Dong Jin Keum, Ji Soo Jang
  • Patent number: 7592864
    Abstract: A low-pass filtering circuit and method are disclosed. The circuit includes a low-pass filter with a capacitor, and a multiplier configured to multiply the capacitance of the capacitor by feeding-back a high-frequency signal apparent in an output signal of the low-pass filter to the capacitor.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: September 22, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Hoon Kang, Seung Chan Heo, Ji Soo Jang, Hui Jung Kim
  • Publication number: 20090185639
    Abstract: A DC offset correction circuit includes a DC offset detector generating a detection voltage based on a result of a comparison of a first reference voltage and a voltage difference between signals input to the DC offset detector, a comparator comparing a second reference voltage and the detection voltage and a third reference voltage and the detection voltage and outputting first and second comparison signals, respectively, as a result of the comparisons, and an up/down counter performing an up or a down count operation in response to one of the first or second comparison signals and, as a result of the up or down count operation, outputting a signal that causes at least one control signal for canceling a DC offset in a signal input to a receiver to be generated.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 23, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ju Young Han, Dong Jin Keum, Ji Soo Jang
  • Publication number: 20080303589
    Abstract: A low-pass filtering circuit and method are disclosed. The circuit includes a low-pass filter with a capacitor, and a multiplier configured to multiply the capacitance of the capacitor by feeding-back a high-frequency signal apparent in an output signal of the low-pass filter to the capacitor.
    Type: Application
    Filed: May 21, 2008
    Publication date: December 11, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hoon KANG, Seung Chan HEO, Ji Soo JANG, Hui Jung KIM
  • Patent number: 7443233
    Abstract: A DC offset canceling apparatus includes a main amplifier, a replica amplifier, a switch, and a storage unit. The replica amplifier has substantially the same structure as the main amplifier, receives an input signal having the same sign as that of a signal input to the main amplifier, and has an output connected to main amplifier with an opposite sign. The switch switches a signal input to the replica amplifier in response to a control signal. The storage unit is connected to an input terminal of the replica amplifier to maintain a DC value for a predetermined period of time when the switch is open.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Soo Jang, Sang-Hoon Kang
  • Publication number: 20070247218
    Abstract: A DC offset canceling apparatus includes a main amplifier, a replica amplifier, a switch, and a storage unit. The replica amplifier has substantially the same structure as the main amplifier, receives an input signal having the same sign as that of a signal input to the main amplifier, and has an output connected to main amplifier with an opposite sign. The switch switches a signal input to the replica amplifier in response to a control signal. The storage unit is connected to an input terminal of the replica amplifier to maintain a DC value for a predetermined period of time when the switch is open.
    Type: Application
    Filed: December 29, 2006
    Publication date: October 25, 2007
    Inventors: Ji-Soo Jang, Sang-Hoon Kang