Abstract: An imaging lens assembly includes a plastic barrel and an optical element set. The optical element set includes an optical lens element, a light blocking sheet and a light-shielding layer. At least one surface of an object-side peripheral surface and an image-side peripheral surface of the optical lens element includes an annular side wall. An annular abutting surface of the light blocking sheet and the annular side wall of the optical lens element are disposed correspondingly to each other. The light-shielding layer surrounds a central opening of the light blocking sheet and includes an annular concave-curved portion. The annular concave-curved portion is for retaining the light blocking sheet, so that there is no relative displacement in a direction parallel to an optical axis between the annular abutting surface of the light blocking sheet and the annular side wall of the optical lens element.

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: The present invention provides a system for data mapping and storing in digital three-dimensional oscilloscope, wherein the fixed coefficients, which are calculated according the parameters and settings of a digital oscilloscope, are stored into a fixed coefficient memory CO RAM, the fixed coefficients are outputted to N fractional operation units through N?1 D flip-flop delay units to multiply with the acquired data x(n) and then be accumulated, thus N fractional calculus results are obtained. In this way, N fractional calculus results can be obtained by performing L/N fractional calculus operations. N fractional calculus results are sent to a signal processing and display module, in which they are converted into a display data through a drawing thread, and the display data are sent to LCD for displaying, thus the fractional calculus operation and display of a input signal in a digital oscilloscope is realized.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Abstract: A random transient power test signal generator based on three-dimensional memristive discrete map, which utilizes a three-dimensional parallel bi-memristor Logistic map module to generate two pseudo-random sequences, and based on the sequences, uses two waveform output modules to generate transient voltage and transient current signals respectively, thus the random transient power testing signal is obtained. The map can significantly improve the complexity of chaos and greatly extend its range of chaos. In addition, a performance evaluation shows the map has more robust hyperchaotic behavior in much larger chaos range. Moreover, the random sequences generated by the map module combines with DDS, which can generate a transient power signal with completely random period, starting phase and ending phase.

Abstract: An optical path folding element includes an optical portion, a connection portion, matte structures and a light blocking layer. The optical portion has an optical surface and two reflective surfaces. A light beam enters into the optical path folding element via the optical surface and is reflected inside the optical path folding element through the optical surface. Each reflective surface is configured to reflect the light beam again inside the optical path folding element. The connection portion has connection surfaces connected to the optical surface and the reflective surfaces. The matte structures are at least disposed on and integrally formed with the connection portion. Each unitary structure of the matte structures is tapered off and recessed from the connection portion, such that the outer surface of the connection portion has an undulating shape. The light blocking layer is at least disposed on the connection portion for blocking light.

Abstract: An augmented reality interaction system applied to a physical scene and comprising a server and a plurality of mobile devices is provided. The server stores a point cloud map corresponding to the physical scene, and one of the mobile devices uploads a physical image, role state variation data and local variation data to the server. The server compares the physical image with the point cloud map to generate orientation data of the mobile device in real time, and adjusts role data corresponding to a user according to the role state variation data and the local variation data. The server pushes the orientation data of the mobile device and the role data to the other mobile devices such that augmented reality images displayed by the other mobile devices are adjusted in real time according to the orientation data of the mobile device and the role data.

Abstract: An artificial tanzanite comprises aluminosilicate and vanadium, wherein the content of the aluminosilicate is in a range from 1 mass % to 30 mass % and the content of the vanadium is in a range from 1000 ppm to 40000 ppm. The artificial tanzanite is prepared by a method comprising: providing a synthetic raw material, wherein the synthetic raw material comprises the aluminosilicate, silicon-containing oxide, vanadium-containing oxide, and calcium-containing salt; and heating the synthetic raw material to a synthetic temperature, and keeping the synthetic raw material under a synthetic pressure to carry out synthetic reaction to form the artificial tanzanite after a period of synthetic time.

Abstract: An addition system of a reducing agent in a semiconductor manufacturing process includes pre-treatment and post-treatment gas concentration detection devices, a process exhaust gas treatment device, a reducing agent supply device, and an addition system control device. The process exhaust gas treatment device purifies exhaust gas of a semiconductor manufacturing process and emits a post-treatment gas. The reducing agent supply device supplies a reducing agent gas into the process exhaust gas treatment device. The post-treatment gas concentration detection device detects a residual concentration of the reducing agent gas in the post-treatment gas. The addition system control device calculates destruction and removal efficiency (DRE) for process gases according to pre-treatment and post-treatment gas concentrations, and, according to the DRE and the residual concentration, sends a signal to the reducing agent supply device to control the amount of the reducing agent gas added.

Abstract: For a manual gearshift control of conventional vehicle transmission, a vehicle gearshift automatic control device including a first actuator module, a second actuator module and an electronic control unit, is provided in an add-on manner to retrofit the vehicle transmission with both automatic and manual gearshift functions. In an automatic gearshift mode, the electronic control unit executes the vehicle gearshift automatic control method and receives an automatic gearshift command to drive the first actuator module to push a shift lever to implement a lateral shift selection, or to drive the second actuator module to spin a park lever to implement a longitudinal gearshift. For vehicle security, whenever a vehicle gearshift automatic control device failure or a manual gearshift intervention is detected in the automatic gearshift mode, the electronic control unit shuts off the automatic gearshift mode and switches to a manual gearshift mode to perform the manual gearshift function.

Abstract: A computer-implemented method, a computer system, and computer program product for associating security events. The method includes obtaining a result of implementation of one or more Locality-Sensitive Hashing (LSH) functions to feature data of a first event detected by a first device. The method also includes mapping the result to one or more positions in a data structure. In response to data elements of the one or more positions indicating first information associating with the one or more positions exists in a storage, the method includes obtaining the first information from the storage. The method further includes sending the first information to the first device.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

Abstract: An imaging lens assembly module has an optical axis, and includes an optical element set, a light blocking element assembling surface, and a light absorbing layer. The optical element set includes an optical lens element and a light blocking sheet. The optical lens element is a plastic lens element, and includes an optical effective portion and an outer peripheral portion. The light blocking sheet is disposed on the outer peripheral portion, and spaced apart from the outer peripheral portion. The light blocking sheet includes an object-side surface, an image-side surface and an inner opening surface. The inner opening surface surrounds a through hole of the light blocking sheet. The light blocking sheet is disposed on the light blocking element assembling surface. The light absorbing layer is disposed on the image-side surface and for fixing the light blocking sheet on the light blocking element assembling surface.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A device incudes a substrate. A first fin and a second fin are over the substrate. An isolation structure is laterally between the first fin and the second fin. A gate structure crosses the first fin and the second fin. A first source/drain epitaxy structure is over the first fin. A second source/drain epitaxy structure is over the second fin. A spacer layer extends from a first sidewall of the first fin to a first sidewall of the second fin along a top surface of the isolation structure.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode structure over a channel region, wherein the gate electrode structure includes a gate dielectric layer disposed over the first channel region, a gate electrode disposed over the gate dielectric layer, and insulating spacers disposed over opposing sidewalls of the gate electrode, wherein the gate dielectric layer is disposed over opposing sidewalls of the gate electrode. An interlayer dielectric layer is formed over opposing sidewalls of the insulating spacers. The insulating spacers are removed from an upper portion of the opposing sidewalls of the gate electrode to form trenches between the opposing sidewalls of the upper portion of the gate electrode and the interlayer dielectric layer, and the trenches are filled with an insulating material.