Abstract: A touch panel module includes a display panel, a polarizing film, a first optical clear adhesive layer, a transparent touch layer, a second optical clear adhesive layer, and a protective layer that are sequentially stacked on the display panel, and a sealing adhesive layer. The first optical clear adhesive layer extends outward from an edge of the polarizing film to form a gap with the display panel. The sealing adhesive layer is formed between the display panel and the protective layer, completely covers sidewalls of the polarizing film, the first optical clear adhesive layer, the transparent touch layer, and the second optical clear adhesive layer on the same side, and fills the gap. After undergoing a temperature shock test, a number of air bubbles with a size larger than 0.1 mm per square centimeter of the touch panel module is less than 1.

Abstract: A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.

Abstract: A reference-free multi-level sensing circuit for computing-in-memory applications is controlled by a first bit line and a second bit line. An encoding unit generates a first register output value and a plurality of encoded values. The first register output value feedback controls a precharging unit so as to enable the precharging unit to precharge one of the first bit line and the second bit line according to the first register output value. A voltage level of the one of the first bit line and the second bit line is lower than a voltage level of the other one of the first bit line and the second bit line. The encoded values and the first register output value are formed a multi-bit signal to estimate voltage levels of the first bit line and the second bit line.

Abstract: A selective bit-line sensing method is provided. The selective bit-line sensing method includes the steps of: generating a neuron weights information, the neuron weights information defines a distribution of 0's and 1's storing in the plurality of memory cells of the memory array; and selectively determining either the plurality of bit-lines or the plurality of complementary bit-lines to be sensed in a sensing operation according to the neuron weights information. When the plurality of bit-lines are determined to be sensed, the plurality of first word-lines are activated by the artificial neural network system through the selective bit-line detection circuit, and when the plurality of complementary bit-lines are determined to be sensed, the plurality of second word-lines are activated by the artificial neural network system.

Abstract: A method and a circuit for generating a reference voltage are provided. The circuit includes: a first column of dummy neurons with weight 0 and a second column of dummy neurons with weight 1, wherein the plurality word-lines are connected to the dummy neurons in the first and second columns, respectively; a bit-line connected to a voltage source and the first column of dummy neurons; a complementary bit-line is connected to the voltage source and the second column of dummy neurons, wherein when the artificial neural network system is operated to sense the neurons of the memory cell array, one or more of the plurality of word-lines are activated, and the corresponding dummy neurons of the first column and the second column are activated to generate the reference voltage at the output end for sensing the neurons of the memory cell array.