Abstract: System and methods are described for generating recommendations from dynamically-mapped data. In one implementation, a database system receives a first request to generate a recommendation objection and a second request to retrieve additional data to include in the recommendation object. The database system retrieves the recommendation data from a first database table. The database system identifies the additional data in a second database table that is stored separately from the first database table. The database system generates the recommendation object to include the recommendation data from the first database, and maps the additional data to one or more fields of the recommendation object.

Abstract: System and methods are described for generating recommendations from dynamically-mapped data. In one implementation, a database system receives a first request to generate a recommendation objection and a second request to retrieve additional data to include in the recommendation object. The database system retrieves the recommendation data from a first database table. The database system identifies the additional data in a second database table that is stored separately from the first database table. The database system generates the recommendation object to include the recommendation data from the first database, and maps the additional data to one or more fields of the recommendation object.

Abstract: System and methods are described for generating recommendations from dynamically-mapped data. In one implementation, a database system receives a first request to generate a recommendation objection and a second request to retrieve additional data to include in the recommendation object. The database system retrieves the recommendation data from a first database table. The database system identifies the additional data in a second database table that is stored separately from the first database table. The database system generates the recommendation object to include the recommendation data from the first database, and maps the additional data to one or more fields of the recommendation object.

Abstract: A module mount interposer may include one or more fastener receivers configured to mechanically couple with one or more fasteners so as to mechanically and electrically couple a module to the interposer. The module mount interposer may also include a core configured to electrically couple with the module, wherein each of the fastener receivers are mechanically coupled to the core. The module mount interposer may additionally include a solder layer electrically coupled to the core and configured to electrically couple with a printed circuit board (PCB) so as to provide an electrical signal from the module to the PCB and to provide an electrical signal from the PCB to the module.

Abstract: A module mount interposer may include one or more fastener receivers configured to mechanically couple with one or more fasteners so as to mechanically and electrically couple a module to the interposer. The module mount interposer may also include a core configured to electrically couple with the module, wherein each of the fastener receivers are mechanically coupled to the core. The module mount interposer may additionally include a solder layer electrically coupled to the core and configured to electrically couple with a printed circuit board (PCB) so as to provide an electrical signal from the module to the PCB and to provide an electrical signal from the PCB to the module.

Abstract: A ferrule-to-lens latch mechanism includes a cover movable with respect to a housing of an optical assembly between an open position in which a cavity defined by the housing is visible and a closed position in which the cavity is covered by the cover. A lens is positioned in the cavity and has one or more guide pins which are visible when the cover is in the open position prior to mating a ferrule to the lens. A spring clip coupled to the housing and positioned in the cavity is configured to allow insertion and removal of the ferrule from the cavity when the cover is in the open position and may bias the ferrule against the lens when the ferrule is mated to the lens. When the ferrule is mated to the lens, the cover may cooperate with the spring clip to inhibit removal of the ferrule.

Abstract: A ferrule-to-lens latch mechanism includes a cover movable with respect to a housing of an optical assembly between an open position in which a cavity defined by the housing is visible and a closed position in which the cavity is covered by the cover. A lens is positioned in the cavity and has one or more guide pins which are visible when the cover is in the open position prior to mating a ferrule to the lens. A spring clip coupled to the housing and positioned in the cavity is configured to allow insertion and removal of the ferrule from the cavity when the cover is in the open position and may bias the ferrule against the lens when the ferrule is mated to the lens. When the ferrule is mated to the lens, the cover may cooperate with the spring clip to inhibit removal of the ferrule.

Abstract: A module mount interposer may include one or more fastener receivers configured to mechanically couple with one or more fasteners so as to mechanically and electrically couple a module to the interposer. The module mount interposer may also include a core configured to electrically couple with the module, wherein each of the fastener receivers are mechanically coupled to the core. The module mount interposer may additionally include a solder layer electrically coupled to the core and configured to electrically couple with a printed circuit board (PCB) so as to provide an electrical signal from the module to the PCB and to provide an electrical signal from the PCB to the module.

Abstract: A module mount interposer may include one or more fastener receivers configured to mechanically couple with one or more fasteners so as to mechanically and electrically couple a module to the interposer. The module mount interposer may also include a core configured to electrically couple with the module, wherein each of the fastener receivers are mechanically coupled to the core. The module mount interposer may additionally include a solder layer electrically coupled to the core and configured to electrically couple with a printed circuit board (PCB) so as to provide an electrical signal from the module to the PCB and to provide an electrical signal from the PCB to the module.

Abstract: A feeding device includes a sliding member, a saddle slidably assembled with the sliding member, a driving module for moving the saddle back and forth relative to the sliding member, a main shaft positioned on the saddle, a cutter positioned with the main shaft, at least one balancing cylinder fixedly coupled with the sliding member and the saddle for balancing the main shaft. The disclosure also supplies a machine tool using the feeding device.

Abstract: Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

Abstract: The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.

Abstract: Functionality can be implemented for optimizing connection constraints in an integrated circuit design. A target timing path associated with a first of a plurality of sub-connections of the integrated circuit is determined. A timing probability value and a route probability value associated with the first of the plurality of sub-connections is determined based, at least in part, on the target timing path associated with the first of the plurality of sub-connections. The timing probability value indicates a probability that timing closure is satisfied on the target timing path. The route probability value indicates a probability that a physical routing track on the target timing path associated with the first of the plurality of sub-connections resolves congestion. A current connection constraint associated with the first of the plurality of sub-connections is modified in accordance with a connection constraint model to which the first of the plurality of sub-connections corresponds.

Abstract: The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.