Patents by Inventor Jia-Ming Lin
Jia-Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996481Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.Type: GrantFiled: May 17, 2021Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Publication number: 20240162094Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.Type: ApplicationFiled: January 5, 2024Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
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Patent number: 11967504Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.Type: GrantFiled: November 22, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yi Lee, Jia-Ming Lin, Kun-Yu Lee, Chi On Chui
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Publication number: 20240096961Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Shih-Chuan CHIU, Tien-Lu LIN, Yu-Ming LIN, Chia-Hao CHANG, Chih-Hao WANG, Jia-Chuan YOU
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Publication number: 20230326967Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Hsin-Yi Lee, Jia-Ming Lin, Chi On Chui
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Patent number: 11715762Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.Type: GrantFiled: April 1, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Yi Lee, Jia-Ming Lin, Chi On Chui
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Publication number: 20230231037Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Patent number: 11610982Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: GrantFiled: January 4, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Publication number: 20220406598Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.Type: ApplicationFiled: November 22, 2021Publication date: December 22, 2022Inventors: Hsin-Yi Lee, Jia-Ming Lin, Kun-Yu Lee, Chi On Chui
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Publication number: 20220238648Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.Type: ApplicationFiled: April 1, 2021Publication date: July 28, 2022Inventors: Hsin-Yi Lee, Jia-Ming Lin, Chi On Chui
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Publication number: 20220085187Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.Type: ApplicationFiled: January 4, 2021Publication date: March 17, 2022Inventors: Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Hsien-Ming Lee, Chi On Chui
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Publication number: 20210175425Abstract: Provided are a method for forming a perovskite layer and a method for forming a structure comprising a perovskite layer. The method for forming a perovskite layer includes the following steps: coating a perovskite precursor material on a substrate; and performing a heating treatment to the substrate; and irradiating the perovskite precursor material with infrared light.Type: ApplicationFiled: December 10, 2019Publication date: June 10, 2021Applicant: Industrial Technology Research InstituteInventors: Shih-Hsiung Wu, Yung-Liang Tung, Kuo-Wei Huang, Pei-Ting Chiu, Hung-Ru Hsu, Jia-Ming Lin
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Patent number: 10957545Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.Type: GrantFiled: November 30, 2018Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin
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Publication number: 20210083048Abstract: A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Ming LIN, Shiu-Ko JANGJIAN, Chun-Che LIN, Ying-Lang WANG, Wei-Ken LIN, Chuan-Pu LIU
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Patent number: 10861701Abstract: A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive.Type: GrantFiled: June 29, 2015Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin
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Patent number: 10854713Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.Type: GrantFiled: January 8, 2018Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu
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Patent number: 10658252Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.Type: GrantFiled: April 22, 2019Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Ming Lin, Wei-Ken Lin, Shiu-Ko JangJian, Chun-Che Lin
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Publication number: 20190252273Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Jia-Ming Lin, Wei-Ken Lin, Shiu-Ko JangJian, Chun-Che Lin
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Patent number: 10269664Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.Type: GrantFiled: October 12, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Ming Lin, Wei-Ken Lin, Shiu-Ko JangJian, Chun-Che Lin