Patents by Inventor Jia-Nan Tai

Jia-Nan Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Light emitting device array circuit capable of reducing ghost image and driver circuit and control method thereof
    Patent number: 11468831
    Abstract: A light emitting device array circuit capable of reducing ghost image includes: a light emitting device array, plural scan line switch circuits, and a driver circuit. The light emitting device array includes plural light emitting devices arranged in plural scan lines and plural data lines. In one frame, plural scan line switch circuits respectively electrically connect plural scan nodes in plural corresponding scan lines to a scan conduction voltage in a non-overlapping sequential order. Data line buffer circuits of the driver circuit provide predetermined dimming levels to corresponding data nodes respectively according to data operation signals. A pre-discharge control amplifier circuit of the driver circuit is coupled to the plural scan nodes and provides a pre-discharge level to at least one predetermined scan node during a predetermined pre-discharge time period according to a pre-discharge signal.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: October 11, 2022
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Heng-Sheng Chao, Jia-Nan Tai, Hsing-Shen Huang
  • Light Emitting Device Array Circuit Capable of Reducing Ghost Image and Driver Circuit and Control Method Thereof
    Publication number: 20220223099
    Abstract: A light emitting device array circuit capable of reducing ghost image includes: a light emitting device array, plural scan line switch circuits, and a driver circuit. The light emitting device array includes plural light emitting devices arranged in plural scan lines and plural data lines. In one frame, plural scan line switch circuits respectively electrically connect plural scan nodes in plural corresponding scan lines to a scan conduction voltage in a non-overlapping sequential order. Data line buffer circuits of the driver circuit provide predetermined dimming levels to corresponding data nodes respectively according to data operation signals. A pre-discharge control amplifier circuit of the driver circuit is coupled to the plural scan nodes and provides a pre-discharge level to at least one predetermined scan node during a predetermined pre-discharge time period according to a pre-discharge signal.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 14, 2022
    Inventors: Heng-Sheng Chao, Jia-Nan Tai, Hsing-Shen Huang