Patents by Inventor Jia-Rui Hu
Jia-Rui Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10163733Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.Type: GrantFiled: May 31, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jia-Rui Hu, Shu-Chuan Chuang, Che-Yuan Sun, Chih-Ming Ke
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Publication number: 20170345725Abstract: A method provides a design layout having a pattern of features. The design layout is transferred onto a substrate on a semiconductor substrate using a mask. A scanning parameter is determined based on the design layout. An image of the substrate is generated using the determined scanning parameter. A substrate defect is identified by comparing a first number of closed curves in a region of the image and a second number of polygons in a corresponding region of the design layout.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: Jia-Rui HU, Shu-Chuan CHUANG, Che-Yuan SUN, Chih-Ming KE
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Patent number: 9418199Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.Type: GrantFiled: March 17, 2015Date of Patent: August 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Rui Hu, Chih-Ming Ke, Hua-Tai Lin, Kai-Hsiung Chen, Tsai-Sheng Gau
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Patent number: 9201022Abstract: In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.Type: GrantFiled: June 2, 2011Date of Patent: December 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Rui Hu, Te-Chih Huang, Chih-Ming Ke, Hua-Tai Lin, Tsai-Sheng Gau
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Publication number: 20150254394Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.Type: ApplicationFiled: March 17, 2015Publication date: September 10, 2015Inventors: Jia-Rui Hu, Chih-Ming Ke, Hua-Tai Lin, Kai-Hsiung Chen, Tsai-Sheng Gau
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Patent number: 8984450Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.Type: GrantFiled: February 14, 2014Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Rui Hu, Kai-Hsiung Chen, Chih-Mihg Ke, Hua-Tai Lin, Tsai-Sheng Gau
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Publication number: 20140282334Abstract: The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.Type: ApplicationFiled: February 14, 2014Publication date: September 18, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Rui Hu, Kai-Hsiung Chen, Chih-Mihg Ke, Hua-Tai Lin, Tsai-Sheng Gau
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Patent number: 8755045Abstract: In one embodiment, a method for detecting design defects is provided. The method includes receiving design data of an integrated circuit (IC) on a wafer, measuring wafer topography across the wafer to obtain topography data, calculating a scanner moving average from the topography data and the design data to provide a scanner defocus map across the wafer, and determining a hotspot design defect from the scanner defocus map. A computer readable storage medium, and a system for detecting design defects are also provided.Type: GrantFiled: January 6, 2012Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyuh-Fuh Lin, Te-Chih Huang, Guo-Tsai Huang, Jia-Rui Hu, Chih-Ming Ke
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Publication number: 20130176558Abstract: In one embodiment, a method for detecting design defects is provided. The method includes receiving design data of an integrated circuit (IC) on a wafer, measuring wafer topography across the wafer to obtain topography data, calculating a scanner moving average from the topography data and the design data to provide a scanner defocus map across the wafer, and determining a hotspot design defect from the scanner defocus map. A computer readable storage medium, and a system for detecting design defects are also provided.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jyuh-Fuh Lin, Te-Chih Huang, Guo-Tsai Huang, Jia-Rui Hu, Chih-Ming Ke
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Publication number: 20120308112Abstract: In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Rui Hu, Te-Chih Huang, Chih-Ming Ke, Hua-Tai Lin, Tsai-Sheng Gau