Abstract: Disclosed are an integrated module and an intelligent device. The integrated module comprises at least one first functional QO module, at least one second functional module, and a PCB. The PCB comprises: a PCB main body, the at least one first functional module being disposed on the PCB main body; and a PCB protruding portion, the PCB protruding portion being disposed on one side of the PCB main body and connected to the PCB main body, and the at least one second functional module being disposed on the PCB protruding portion.

Abstract: This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index.

Abstract: This disclosure provides an instruction transmitting unit, an instruction execution unit, and a related apparatus and method. The instruction transmitting unit includes: an instruction splitter adapted to split a to-be-executed vector instruction into microinstructions; a microinstruction index fetcher adapted to acquire a number-of-effective-elements index of the microinstructions resulting from the splitting based on an element range involved in the microinstructions; an index comparison subunit adapted to compare the acquired number-of-effective-elements index with a first index, where the first index is a number-of-effective-elements index of a fault-only-first microinstruction whose processing has not been completed; and a microinstruction transmission controller adapted to transmit the microinstructions resulting from the splitting to a vector execution unit for execution when the number-of-effective-elements index is less than the first index.

Abstract: The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag.

Abstract: The present disclosure discloses an instruction processing apparatus, comprising a first vector register adapted to store a first vector to be operated on, a second vector register adapted to store a second vector to be operated on, a decoder adapted to receive and decode a data splicing instruction, and an execution unit. The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, a splicing indicator, and a destination.

Abstract: The present disclosure discloses an instruction processing apparatus, comprising a first vector register adapted to store a first vector to be operated on, a second vector register adapted to store a second vector to be operated on, a decoder adapted to receive and decode a data splicing instruction, and an execution unit. The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, a splicing indicator, and a destination.

Abstract: The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag.

Abstract: The present invention discloses an instruction processing device, including a first register adapted to store a source data address, a second register adapted to store a source data length, a third vector register adapted to store target data, a decoder and an execution unit. The decoder is adapted to receive and decode a data loading instruction. The data loading instruction instructs that the first register serves as a first operand, the second register serves as a second operand, and the third vector register serves as a third operand.

Abstract: The invention discloses a toilet brush. The toilet brush comprises a handle and a brush head connected with the handle, wherein the brush head comprises a brush head body and a brush head sleeve, the surface of the brush head body is sleeved with the brush head sleeve, the brush head sleeve comprises a brush head sleeve body and a plurality of bristles uniformly distributed on the outer surface of the brush head sleeve body, and the brush head sleeve is a latex brush head sleeve or a silica gel brush head sleeve. The bristles of the toilet brush provided by the invention do not deform after being used for many times, and have a long service life. The invention further provides a toilet brush set.