Patents by Inventor Jiajia Yu

Jiajia Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11454852
    Abstract: The present application provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a substrate, a driving circuit layer located on the substrate, and a pixel electrode layer located on the driving circuit layer, wherein the pixel electrode layer is electrically connected to the driving circuit layer through a first via hole; and wherein the pixel electrode layer further includes at least one second via hole located in the first via hole, and the second via hole exposes a part of the driving circuit layer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 27, 2022
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jiajia Yu
  • Publication number: 20210405477
    Abstract: The present application provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a substrate, a driving circuit layer located on the substrate, and a pixel electrode layer located on the driving circuit layer, wherein the pixel electrode layer is electrically connected to the driving circuit layer through a first via hole; and wherein the pixel electrode layer further includes at least one second via hole located in the first via hole, and the second via hole exposes a part of the driving circuit layer.
    Type: Application
    Filed: February 25, 2020
    Publication date: December 30, 2021
    Inventor: Jiajia YU
  • Patent number: 11075064
    Abstract: An amplification system includes a first amplification module, a second amplification module, a third amplification module I, a fourth amplification module I, a first load, a third amplification module II, a fourth amplification module II and a second load. An output terminal of the first amplification module is connected to an input terminal of the second amplification module; output terminals of the second amplification module are connected to an input terminal of the third amplification module I and an input terminal of the third amplification module II. An output terminal of the third amplification module I is connected to an input terminal of the first load through the fourth amplification module I. An output terminal of the third amplification module II is connected to an input terminal of the second load through the fourth amplification module II.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 27, 2021
    Assignee: SHANGHAI YUDA INDUSTRIAL CO., LTD.
    Inventors: Bing Xue, Jian Jiang, Jiajia Yu, Xiaojun Qi, Bo Hu
  • Publication number: 20200388476
    Abstract: An amplification system includes a first amplification module, a second amplification module, a third amplification module I, a fourth amplification module I, a first load, a third amplification module II, a fourth amplification module II and a second load. An output terminal of the first amplification module is connected to an input terminal of the second amplification module; output terminals of the second amplification module are connected to an input terminal of the third amplification module I and an input terminal of the third amplification module II. An output terminal of the third amplification module I is connected to an input terminal of the first load through the fourth amplification module I. An output terminal of the third amplification module II is connected to an input terminal of the second load through the fourth amplification module II.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 10, 2020
    Applicant: SHANGHAI YUDA INDUSTRIAL CO., LTD.
    Inventors: Bing XUE, Jian JIANG, Jiajia YU, Xiaojun QI, Bo HU
  • Patent number: 9767024
    Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Yong Wu, Xiao Dong Lin, Jiajia Yu, Xueliang Zhong
  • Publication number: 20160321178
    Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.
    Type: Application
    Filed: December 18, 2014
    Publication date: November 3, 2016
    Applicant: Intel Corporation
    Inventors: Yong Wu, Xiao Dong Lin, Jiajia Yu, Xueliang Zhong