Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.

Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.

Abstract: A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor.

Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.

Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.

Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.

Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.

Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.

Abstract: A flexible display panel and device are provided. Data connection touch lines bypass a camera module to electrically couple the data lines at the two sides of the camera module together. Light emitting display can be achieved in a non-display region, thereby increasing a light emitting display area of the flexible display panel.

Abstract: A flexible display panel and device are provided. Data connection touch lines bypass a camera module to electrically couple the data lines at the two sides of the camera module together. Light emitting display can be achieved in a non-display region, thereby increasing a light emitting display area of the flexible display panel.

Abstract: A touch array substrate and a touch panel are provided and the touch array substrate has a substrate, an organic electroluminescent pixel unit layer disposed on the substrate, wherein the organic electroluminescent pixel unit layer has an anode layer, a light emitting layer, and a cathode layer, all of which are stacked in sequence. The cathode layer consists of a plurality of sub-cathodes disposed at intervals, and the sub-cathodes are electrically connected to each other.

Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.

Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.

Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.

Abstract: The present invention provides a touch panel wire arrangement circuit, the touch panel wire arrangement circuit comprises: an ITO region, metal wires, a touch control hole and an integrated circuit; the touch panel wire arrangement circuit further comprises: a rear end switch set, and the rear end switch set comprises: a plurality of switches, and a G electrode of each switch in the plurality of switches is inputted with a switch signal, and D electrodes of the plurality of switches are sequentially coupled to rear ends of the metal wires, and S electrodes of the plurality of switches are inputted with at least one voltage signals; the switch signal is: a signal at high voltage level as a touch panel TP signal does not function; the voltage signal is a common voltage V-com signal as the touch panel is in a display state.

Abstract: An embedded touch panel and the manufacturing method thereof are disclosed. The embedded touch panel includes a TFT substrate, a liquid crystal layer, a color filter, a polarizer and a glass cover arranged in sequence, wherein the polarizer is a non-conductive polarizer. A transparent conductive layer is arranged between the polarizer and the color filter. The TFT substrate includes at least one grounded pin, and the transparent conductive layer electrically connects with the grounded pin on the TFT substrate. In view of the above, the transparent conductive layer and the non-conductive polarizer may replace the high impedance polarizer of the embedded touch panel so as to greatly reduce the manufacturing cost. In addition, by bonding the frame of the polarizer, the bubble issue occurring when bonding the polarizer may be avoided.