Patents by Inventor Jian-Hung Lee

Jian-Hung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978511
    Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
  • Publication number: 20150194433
    Abstract: A field-effect transistor (FET) based one-time programmable (OTP) device is discussed. The OTP device includes a fin structure, a gate structure, a first contact region, and a second contact region. The first contact region includes an insulating region and a conductive region and is configured to be electrically isolated from the gate structure. While, the second contact region includes the conductive region and is configured to be electrically coupled to at least a portion of the gate structure. The OTP device is configured to be programmed by disintegration of the insulating region in response to a first voltage being applied to the first contact and a second voltage being applied to the second contact region simultaneously, where the second voltage is higher than the first voltage by a threshold value.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 9, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Shom PONOTH, CHANGYOK PARK, JIAN-HUNG LEE, CHAO-YANG LU, GUANG-JYE SHIAU
  • Patent number: 8921938
    Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xin Yi Zhang, Weidan Li, Chuan-Cheng Cheng, Jian-Hung Lee, Chung Chyung (Jason) Han