Patents by Inventor Jian-Jou LIAN
Jian-Jou LIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194522Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Patent number: 11996470Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.Type: GrantFiled: July 26, 2022Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
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Patent number: 11990339Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.Type: GrantFiled: August 2, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
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Patent number: 11978801Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.Type: GrantFiled: July 26, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Chun-Neng Lin, Chieh-Wei Chen, Tzu-Ang Chiang, Ming-Hsi Yeh
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Publication number: 20240105818Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
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Patent number: 11942362Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: GrantFiled: March 6, 2023Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Publication number: 20240063060Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Chun-Neng Lin, Ming-Hsi Yeh
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Patent number: 11901441Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.Type: GrantFiled: February 10, 2023Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen
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Patent number: 11855193Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.Type: GrantFiled: January 17, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Jou Lian, Chun-Neng Lin, Ming-Hsi Yeh, Chieh-Wei Chen, Tzu-Ang Chiang
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Publication number: 20230411206Abstract: A method for manufacturing a semiconductor device includes: forming a patterned dielectric layer over a substrate, the patterned dielectric layer including an interconnect opening having a sidewall surface and a bottom surface; and forming a doped film by an opening-adjustment process, the doped film being disposed on the patterned dielectric layer and extending into the interconnect opening to cover an upper portion of the sidewall surface, so as to adjust a profile of the interconnect opening.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Neng LIN, Jian-Jou LIAN, Chieh-Wei CHEN
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Patent number: 11848239Abstract: A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.Type: GrantFiled: July 10, 2020Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Chun-Neng Lin, Ming-Hsi Yeh
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Publication number: 20230369494Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHUN-NENG LIN, JIAN-JOU LIAN, MING-HSI YEH
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Patent number: 11817330Abstract: A method for processing a substrate is provided. The method includes the following operations: placing a substrate over a first injector in a substrate processing apparatus, the substrate having a front surface and a back surface opposite to the front surface, and the front surface having a plurality of concentric regions; adjusting a temperature of each of the plurality of concentric regions by controlling at least one of a flow rate and a temperature associated with a fluid dispensing from the first injector; and rotating the substrate by a spin base disposed below the substrate, the substrate is rotated with respect to a center axis perpendicular to the front surface thereof when adjusting the temperature. The spin base includes a ring opening for rotating relative to the first injector, and the first injector is displaced from a projection of a center of the substrate from a top view perspective.Type: GrantFiled: July 21, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Po-Yuan Wang, Tzu Ang Chiang, Jian-Jou Lian, Yu Shih Wang, Chun-Neng Lin, Ming-Hsi Yeh
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Publication number: 20230352306Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.Type: ApplicationFiled: June 29, 2023Publication date: November 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
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Publication number: 20230327002Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Wei CHEN, Jian-Jou LIAN, Tzu-Ang CHIANG, Po-Yuan WANG, Yu-Shih WANG, Chun-Neng LIN, Ming-Hsi YEH
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Methods of forming a semiconductor device with a gate structure having a dielectric protection layer
Patent number: 11749753Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.Type: GrantFiled: June 15, 2020Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chun-Neng Lin, Jian-Jou Lian, Ming-Hsi Yeh -
Patent number: 11735425Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.Type: GrantFiled: March 7, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Jian-Jou Lian, Po-Yuan Wang, Chieh-Wei Chen
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Patent number: 11735426Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.Type: GrantFiled: August 13, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURINGInventors: Jian-Jou Lian, Li-Min Chen, Neng-Jye Yang, Ming-Hsi Yeh, Shun Wu Lin, Kuo-Bin Huang
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Publication number: 20230207384Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Jian-Jou Lian, Kuo-Bin Huang, Neng-Jye Yang, Li-Min Chen
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Publication number: 20230187543Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jian-Jou Lian, Tzu Ang Chiang, Ming-Hsi Yeh, Chun-Neng Lin, Po-Yuan Wang, Chieh-Wei Chen