Abstract: A read/write collision-free static random access memory which can perform read/write operations simultaneously without read/write collisions. The static random access memory includes a plurality of memory cells and its features are that the memory cells are divided into several memory banks wherein each bank has independent reading and writing paths. The number of memory cells for each memory bank can be determined by a specific length of memory cells between some memory cells undergoing reading operation and other memory cells undergoing writing operation, and by the reading speed of said reading operation and the writing speed of the writing operation, whereby the reading operation and the writing operation read and write to two different memory banks of the static random access memory at the same time such that read/write collisions can be prevented.

Abstract: A single-port SRAM with no read/write collisions. The present invention uses some X-axis and Y-axis control circuits to reduce the amounts of lines used in the structure of the present invention, but still maintains circuitry stability.

Abstract: The continuing need for faster and denser SRAM memories places a constant increased demand on the power consumption of the memory devices. Much of the power consumption occurs during the pre-charge phase where it is common practice to bring up all pre-charge circuits at once and hold them active until the memory operations are complete. This invention describes a design where each pre-charge circuit connected to a group of memory cells through bit lines is activated at a separate time from the other pre-charge circuits. Thus each pre-charge circuit is active only during the time that useful work is being done with that portion of the memory. This reduces power consumption by not powering on circuits and precharging bit lines before they are actually needed.