Abstract: A scheduling method and apparatus for a distributed computing system are disclosed. The method includes: dividing, at a first processing stage, data that needs to be processed in a task into N data blocks BN; processing, if the data block BN obtained after the division meets a requirement that is in a second processing stage and for task balance in the second processing stage, data of a same key according to a same function in the second processing stage; and allocating a resource to each task in the second processing stage to perform scheduling. In this way, because a data block is divided into relatively small data blocks and processing time is mostly within a controllable range, scheduling fairness can be improved; when data is divided into data blocks of relatively small capacity, sufficient concurrent jobs can also be ensured, and concurrency of the distributed computing system can be enhanced.

Abstract: A fast installation structure on a faucet table, comprising: a table plane and a bottom seat. The bottom seat is disposed on the table plane, and is used to install a faucet, including: a connection tube; a lock tight device, disposed and screwed around the connection tube; and at least two position holding block, disposed at a lower portion of the connection tube, and are repulsive to each other magnetically. The lock tight device is a lock tight ring or a lock tight screw. The outer threads are provided on the connection tube, while inner threads are provided on the lock tight ring, such that the lock tight ring and the connection tube are connected through threading. At least two installation slots are disposed symmetrically at a lower portion of the connection tube, for receiving the position holding blocks.

Abstract: The present application discloses the identification of novel I. orientalis ADH1, ADHa, and ADHb genes, and the production and characterization of genetically modified yeast cells in which these genes were altered. Provided herein are isolated I. orientalis ADH1, ADHa, and ADHb polynucleotides and polypeptides, genetically modified yeast cells that overexpress I. orientalis ADH1 and/or contain deletions or disruptions of ADHa and/or ADHb, and methods of using culturing these modified cells to produce ethanol.

Abstract: A device includes a transformer, a controller, and a switch coupled between the transformer and the controller. The transformer has a primary coil and a secondary coil. The controller receives an indication of a metric of a cell of a battery. In response to the indication, the controller outputs a signal to select a polarity of a balancing current for balancing the cell. The switch receives the signal from the controller. In response to the signal, the switch causes the transformer to generate a primary current of a selected polarity through the primary coil. The transformer generates the balancing current through the secondary coil by inductively coupling the primary coil to the secondary coil. The transformer outputs the balancing current having the polarity for balancing the cell.

Abstract: The present application discloses the identification of the novel K. marxianus xylose transporter genes KHT105 and RAG4, as well as the identification of a novel set of I. orientalis pentose phosphate pathway genes The present application further discloses a series of genetically modified yeast cells comprising various combinations of arabinose fermentation pathways, xylose fermentation pathways, pentose phosphate pathways, and/or xylose transporter genes, and methods of culturing these cells to produce ethanol in fermentation media containing xylose.

Abstract: The present application discloses the identification of the novel K. marxianus xylose transporter genes KHT105 and RAG4, as well as the identification of a novel set of I. orientalis pentose phosphate pathway genes The present application further discloses a series of genetically modified yeast cells comprising various combinations of arabinose fermentation pathways, xylose fermentation pathways, pentose phosphate pathways, and/or xylose transporter genes, and methods of culturing these cells to produce ethanol in fermentation media containing xylose.

Abstract: An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch. The gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in the first channels is driven using a voltage from the first boost capacitor. The gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in the second channels is driven using a voltage from the second boost capacitor. The transistor switch in each channel may include first and second transistors having their sources coupled together, and each of the channels may further include a pull-down switch configured to pull the sources of the first and second transistors to ground.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.

Abstract: In some embodiments, in a method for considering in-phase grouping for a voltage-dependent design rule, for a first net and a second net in a schematic, first data for obtaining the differences between first voltage values of the first and second nets, and between second voltage values of the first and second nets is provided. For each of the first and second nets, the first voltage value is larger than the second voltage value. A layout for the schematic is generated. In the layout, a relationship of a first shape and a second shape associated with the first and the second nets, respectively, is defined using the first data.

Abstract: An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch. The gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in the first channels is driven using a voltage from the first boost capacitor. The gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in the second channels is driven using a voltage from the second boost capacitor. The transistor switch in each channel may include first and second transistors having their sources coupled together, and each of the channels may further include a pull-down switch configured to pull the sources of the first and second transistors to ground.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.

Abstract: A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.

Abstract: The present application discloses the identification of the novel K. marxianus xylose transporter genes KHT105 and RAG4, as well as the identification of a novel set of I. orientalis pentose phosphate pathway genes The present application further discloses a series of genetically modified yeast cells comprising various combinations of arabinose fermentation pathways, xylose fermentation pathways, pentose phosphate pathways, and/or xylose transporter genes, and methods of culturing these cells to produce ethanol in fermentation media containing xylose.

Abstract: The present application discloses the identification of novel I. orientalis ADH1, ADHa, and ADHb genes, and the production and characterization of genetically modified yeast cells in which these genes were altered. Provided herein are isolated I. orientalis ADH1, ADHa, and ADHb polynucleotides and polypeptides, genetically modified yeast cells that overexpress I. orientalis ADH1 and/or contain deletions or disruptions of ADHa and/or ADHb, and methods of using culturing these modified cells to produce ethanol.

Abstract: Disclosed are recombinant microorganisms for producing organic acids. The recombinant microorganisms express a polypeptide that has the enzymatic activity of an enzyme that is utilized in the pentose phosphate cycle. The recombinant microorganism may include recombinant Actinobacillus succinogenes that has been transformed to express a Zwischenferment (Zwf) gene. The recombinant microorganisms may be useful in fermentation processes for producing organic acids such as succinic acid and lactic acid. Also disclosed are novel plasmids that are useful for transforming microorganisms to produce recombinant microorganisms that express enzymes such as Zwf.

Abstract: A video analysis technique includes correlating frames from a processed video with frames from a pre-processed, original video. A linear approximation of a relationship between the correlated frames is determined. A disclosed example includes determining a linear approximation that maximizes the number of processed video frames that fit into the linear approximation. The linear approximation and whether any frames do not fit within the linear approximation is then used to provide quality information for analyzing a quality of the processed video.

Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. A structure includes a target diffusion region including a first edge with a first length and a second edge with a second edge perpendicular to the first length.

Abstract: A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.

Abstract: The present invention relates to a single-stage zero-current switching driving circuit for ultrasonic motor, which comprises: a buck-boost converter and a zero-current switching resonant inverter. The driving circuit according to the present invention integrates the buck-boost converter and the resonant inverter into a single-stage structure, so that the buck-boost converter and the resonant inverter share an active switch and a trigger signal, and therefore, the circuit is simplified and the loss caused by stage switching is reduced. Moreover, the buck-boost converter operates in a discontinuous-conduction mode (DCM), which allows the circuit to have high power factor, and enables the active switch to be capable of zero-current switching (ZCS), so that the loss caused by switching is largely reduced. In the driving circuit according to the present invention, there's no interaction of power between the buck-boost converter and the resonant inverter, so that the two circuits can be analyzed individually.

Abstract: A method for transferring inorganic oxide nanoparticles from aqueous phase to organic phase. A modifier is used to change the surface polarity of inorganic oxide nanoparticles, followed by using proper solvents to transfer the modified inorganic oxide nanoparticles form aqueous phase to organic phase. The organic dispersion of modified inorganic oxide nanoparticles can be combined with a polymer to provide a polymer composite with the nanoparticles uniformly dispersed therein.