Abstract: A thin film transistor and a manufacturing method therefor, an array substrate, and a display panel and device. The thin film transistor includes: a gate (11) and an active layer (12) that are located on one side of a base substrate (10); a gate insulation layer (13) located between the gate (11) and the active layer (12); and a source (14) and a drain (15) that are spaced apart and both are in contact with the active layer (12), wherein a first ratio of the thickness of the gate insulation layer (13) and the thickness of the active layer (12) ranges from 3 to 4.

Abstract: A display substrate has an active area which includes a photosensitive region with a light-transmitting channel. The display substrate includes a base, a pixel circuit layer, a first insulating layer and a conductive light-shielding layer. The pixel circuit layer includes pixel circuits and at least one pixel circuit includes a first thin film transistor and a second thin film transistor. The first insulating layer has a first via hole. The conductive light-shielding layer includes a conductive light-shielding pattern that has a first light-transmitting hole. Orthogonal projections of the first light-transmitting hole and of a gap region between the first thin film transistor and the second thin film transistor have a first overlapping region, which the light-transmitting channel penetrates. The conductive light-shielding pattern is coupled with a source electrode or a drain electrode of the first thin film transistor through the first via hole.

Abstract: A method for sensing a display panel includes: sensing an electrical characteristic parameter of a driving transistor of a pixel circuit of a sub-pixel in an X-th row in a blank stage between an N-th frame and an (N+1)-th frame, wherein X is a random number, and both N and X are positive integers.

Abstract: A data driving integrated circuit includes a digital-to-analog converter configured to receive a respective digital data signal from a timing controller and convert the respective digital data signal to a respective analog data signal, which is output to a display panel through a respective data line; an analog-to-digital converter configured to receive a respective analog sensing signal from a respective sensing line in the display panel and convert respective analog sensing signal to a respective digital sensing signal, which is output to the timing controller; a first sensing switch configured to control a connection between a first reference voltage line and the respective sensing line; a second sensing switch configured to control a connection between a second reference voltage line and the respective sensing line; and a third sensing switch configured to control the connection between the analog-to-digital converter and the respective sensing line.

Abstract: A liquid crystal display panel includes an array substrate and an opposite substrate that are disposed opposite to each other; the liquid crystal display panel has a display region and at least one non-display region disposed beside the display region. The array substrate is of a multi-layer structure and includes a pixel electrode layer and a plurality of protrusions disposed in the at least one non-display region, and the opposite substrate includes a common electrode layer. A protrusion has a structure including at least one film, and a film of the at least one film is located in a layer included in the array substrate.

Abstract: The present disclosure relates to a driving unit, including a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit includes first switching elements, configured to output a first signal to the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit includes one or more second switching elements, and at least one of the second switching elements is configured to output a second signal to the driving unit in response to the control signal. The driving control circuit is configured to output the control signal at a control signal output terminal. Each of the first switching elements and second switching elements includes a transistor. Control signal input terminals of the first switching elements are coupled to the control signal output terminal through a control signal input line having a ring structure.

Abstract: An array substrate and a display device are disclosed.

Abstract: The disclosure relates to the technical field of display, and discloses an electrode structure, a capacitor, a GOA circuit, an array substrate, a display panel and a display device, wherein the electrode structure includes a body and a first opening formed in the body, the first opening has a half-enclosed shape, and a part, enclosed by the first opening, of the body has a tip structure. Each of the capacitor, the GOA circuit, the array substrate, the display panel and the display device includes the above-mentioned electrode structure.

Abstract: A liquid crystal display panel includes an array substrate and an opposite substrate that are disposed opposite to each other; the liquid crystal display panel has a display region and at least one non-display region disposed beside the display region. The array substrate is of a multi-layer structure and includes a pixel electrode layer and a plurality of protrusions disposed in the at least one non-display region, and the opposite substrate includes a common electrode layer. A protrusion has a structure including at least one film, and a film of the at least one film is located in a layer included in the array substrate.

Abstract: A display device includes: a display panel; a housing configured to support and protect the display panel; a bracket disposed between the display panel and the housing; a plurality of sensors fixed on the bracket; a window located in the display panel or in the housing, and configured to expose at least one of the plurality of sensors; and a driver configured to control the bracket to rotate in a plane parallel to the display panel, and to control the bracket to stop rotating when a required sensor rotates to a position of the window.

Abstract: Disclosed in the present invention are a method and an apparatus for identification of imaging quality of fetal ultrasound images, the method including: acquiring parameters of fetal ultrasound images, used for identification of imaging quality of fetal ultrasound images; identifying an imaging score of fetal ultrasound images based on the parameters thereof; and identifying the imaging quality thereof based on the imaging score thereof. Obviously, it may lead to a quick and accurate identification of the imaging quality of fetal ultrasound images by automatically identifying the imaging quality thereof based on the imaging score thereof, thereby realizing quick and accurate management of the imaging quality thereof so as to facilitate to acquire fetal ultrasound images with high quality, which facilitates the acquisition of accurate fetal growth and development and may have an acknowledgment of the operational standardization of the personnel during the detection of fetal ultrasound images.

Abstract: Disclosed in the present invention are a method and apparatus for the identification of fetal cross-sections based on ultrasound dynamic images; the method includes: inputting sequentially each frame of fetal ultrasound images from acquired multiple consecutive frames of fetal ultrasound images into a predetermined feature-detecting model for analysis; acquiring a sequentially exported analysis from the feature-detecting model as feature information for each frame of fetal ultrasound images; corresponding to each frame of fetal ultrasound images, identifying a cross-section by the categories of the part and the structural feature.

Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.

Abstract: A display driving method and a display device. The display driving method includes: scanning a plurality of subpixels arranged in an N×M array one row by one row or multiple rows by multiple rows to turn on each row of scanned subpixels, so that two adjacent rows of sub-pixels are simultaneously in an on-state for a duration greater than or equal to twice a unit scanning time, the unit scanning time is a time required to scan one row of sub-pixels, wherein N and M are both integers greater than 1; applying data signals to at least two rows of sub-pixels that are simultaneously in the on-state, such that at least a portion of rows of sub-pixels are applied with data signals for a duration greater than the unit scanning time.

Abstract: A display panel includes first signal lines, second signal lines, first conductive patterns, second conductive patterns, at least one first switching unit and at least one second switching unit. An area of the first signal line is greater than that of the second signal line. Each first signal line is electrically connected to at least one first conductive pattern through at least one first switching unit. Each second signal line is electrically connected to at least one second conductive pattern through at least one second switching unit. The first switching unit includes at least one first thin film transistor, and the second switching unit includes at least one second thin film transistor. A channel width-to-length ratio of each first thin film transistor is greater than that of each second thin film transistor.

Abstract: The disclosure relates to the technical field of display, and discloses an electrode structure, a capacitor, a GOA circuit, an array substrate, a display panel and a display device, wherein the electrode structure includes a body and a first opening formed in the body, the first opening has a half-enclosed shape, and a part, enclosed by the first opening, of the body has a tip structure. Each of the capacitor, the GOA circuit, the array substrate, the display panel and the display device includes the above-mentioned electrode structure. By using the above-mentioned electrode structure, electrostatic charge accumulated in the body of the electrode structure can be discharged inside the electrode structure, thus avoiding electrostatic charge accumulation in the electrode structure and preventing the electrode structure from discharging to surrounding circuits so as to avoid damaging the surrounding circuits.

Abstract: The present disclosure relates to a driving unit. The driving unit may include a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit may include a plurality of first switching elements, and at least some of the plurality of first switching elements may be configured to output a first signal to a first output terminal of the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit may include one or more second switching elements, and at least one of the one or more second switching elements may be configured to output a second signal to a second output terminal of the driving unit in response to the control signal from the driving control circuit. The driving control circuit may be configured to output the control signal at a control signal output terminal.

Abstract: An array substrate (10) and a display device (16) are provided, and the array substrate includes a base substrate (1) and includes a pixel array (1) and an auxiliary conductive structure (3) which are on the base substrate (1); the pixel array includes a plurality of pixel units (2) arranged in an array and a plurality of pixel electrodes (21), and each of the plurality of pixel units (2) includes at least one of the plurality of pixel electrodes (21); the auxiliary conductive structure (3) surrounds at least one of the plurality of pixel electrodes (21) and is insulated from the plurality of pixel electrodes (21); a resistivity of a material of the auxiliary conductive structure (3) is less than or equal to a resistivity of a material of the at least one of the plurality of the pixel electrodes (21).

Abstract: An array substrate and a display device are disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.

Abstract: A display panel and a display device are provided. The display panel includes: a substrate, a plurality of pixel units, a functional signal line, and a first conductive structure. The substrate includes a display area and a peripheral area on at least one side of the display area, the plurality of pixel units are in the display area, each pixel unit includes a light-emitting unit and a pixel circuit structure for providing a driving current to the light-emitting unit, and the light-emitting unit is an electroluminescent element. The functional signal line is connected with the pixel circuit structure of each pixel unit and provides a common voltage signal for the pixel circuit structure. The first conductive structure is connected in parallel with the functional signal line and is located at a layer different from that of the functional signal line.