Patents by Inventor Jianbo Xiang

Jianbo Xiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11500650
    Abstract: An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 15, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jianbo Xiang, Bo Zhang
  • Publication number: 20210294615
    Abstract: An FPGA upgrade method is provided, including: delivering, by a host, an upgrade instruction to an FPGA; uninstalling a PCIe driver corresponding to the FPGA to let a status of the PCIe link be changed to link down; continuously monitoring, in a first expiration time, whether the status of the PCIe link is changed to link up; and if yes, reloading the PCIe driver. The method further includes: after the FPGA receives the upgrade instruction, continuously monitoring, in a second expiration time, whether the status of the PCIe link is changed to link down, if yes, loading the configuration data from the FPGA configuration memory for upgrade; and after upgrade is completed, negotiating, by the FPGA, with the host to restore the status of the PCIe link to link up that is used for reloading the PCIe driver upon detection by the host.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Jianbo XIANG, Bo ZHANG
  • Publication number: 20210211728
    Abstract: An image parallel compression method includes dividing data obtained after a discrete cosine transform (DCT) is performed on raw image data or data obtained after Huffman decoding is performed on image data of a joint photographic experts group (JPEG) format, or the like into several sub-blocks on a block basis, and then performing parallel operations such as intra-frame prediction, and arithmetic coding, to implement image parallel compression.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Kangwen Luo, Qunyu Ye, Jianmin Huang, Jianbo Xiang