Patents by Inventor Jiancheng Hu

Jiancheng Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11882682
    Abstract: Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: January 23, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jiancheng Hu
  • Publication number: 20220140071
    Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: forming a plurality of lower electrodes on a base, the lower electrode including a ring-like wall and a petal-like wall extending along a direction perpendicular to a surface of the base, and the petal-like wall dividing the ring-like wall internally into a plurality of discrete first openings; forming a dielectric layer on a bottom and a sidewall of the first opening; and forming an upper electrode in the first opening, the dielectric layer being located between the lower electrode and the upper electrode. The lower electrode according to the present application includes the ring-like wall and the petal-like wall, so that a surface area of the lower electrode is increased.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Inventor: Jiancheng HU
  • Publication number: 20220077146
    Abstract: The embodiments of the present application relate to the field of semiconductor technologies, and disclose a semiconductor structure manufacturing method. The method includes: forming a hard mask on a semiconductor substrate; forming a photoresist film on the hard mask; patterning the photoresist film to form a patterned photoresist layer having first openings and second openings, wherein the second openings are disposed at intervals between the first openings; etching the hard mask by taking the patterned photoresist layer as a mask to form a patterned hard mask layer having a plurality of third openings, wherein the third openings correspond to the first openings and the second openings; and etching the semiconductor substrate by taking the patterned hard mask layer as a mask to form holes along the third openings. According to this method, the manufacturing efficiency and the quality of the holes are improved simultaneously.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventors: Jiancheng HU, MingHung Hsieh
  • Publication number: 20220037333
    Abstract: Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.
    Type: Application
    Filed: August 18, 2021
    Publication date: February 3, 2022
    Inventor: Jiancheng HU
  • Patent number: 8900845
    Abstract: Mutant KSR proteins are disclosed. The mutants include single amino acid substitutions, leading to either a loss of kinase activity or a loss of scaffolding activity. Also disclosed are methods of screening compounds for inhibitors of KSR kinase activity or KSR scaffolding activity. In some embodiments, the screening methods include protein complementation assays in which nucleic acids encoding fusion constructs comprising enzyme portions and kinase dimerization domains are expressed in cells. Inhibitors of dimerization can be indicated by loss of enzyme activity.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 2, 2014
    Assignee: Washington University
    Inventors: Andrey Shaw, Jiancheng Hu, Haiyang Yu
  • Publication number: 20120202233
    Abstract: Mutant KSR proteins are disclosed. The mutants include single amino acid substitutions, leading to either a loss of kinase activity or a loss of scaffolding activity. Also disclosed are methods of screening compounds for inhibitors of KSR kinase activity or KSR scaffolding activity. In some embodiments, the screening methods include protein complementation assays in which nucleic acids encoding fusion constructs comprising enzyme portions and kinase dimerization domains are expressed in cells. Inhibitors of dimerization can be indicated by loss of enzyme activity.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 9, 2012
    Applicant: WASHINGTON UNIVERSITY
    Inventors: Andrey Shaw, Jiancheng Hu, Haiyang Yu