Abstract: A digital filter or a receiver including a digital filter having at least two multiple stage shift registers. A plurality of multipliers corresponding in number to the number of stages in the at least two multiple stage shift registers receive as a first input an output from a corresponding stage of the at least two multiple stage shift registers. A tap weight shifter is coupled to a tap weight source to receive tap weights. The tap weight shifter is coupled to provide a second input to each multiplier. Each multiplier produces an output that is the product of inputs thereto. An adder sums the multiplier outputs to provide a sum output. The tap weight shifter then circularly shifts the tap weights and another multiply-add operation occurs. Several shift/multiply/add cycles may occur before data is again shifted into the at least two multiple stage shift registers, and another multiply-add operation occurs.

Abstract: A linear intrasummed multiple-bit feedback shift register is presented which comprises a multi-stage multi-bit feedback shift register and further includes an adder situated before the input to each stage and which is used to modify the shifted signals according to predefined constants. The additional intrastage summing increases the complexity of the feedback function and makes it more difficult to determine the specific structure from a limited stream of output bits, thus increasing the security of the circuit.

Abstract: There is disclosed a digital filter or a receiver including a digital filter having at least two multiple stage shift registers. A plurality of multipliers corresponding in number to the number of stages in the at least two multiple stage shift registers receive as a first input an output from a corresponding stage of the at least two multiple stage shift registers. A tap weight shifter is coupled to a tap weight source to receive tap weights. The tap weight shifter is coupled to provide a second input to each multiplier. Each multiplier produces an output that is the product of inputs thereto. An adder sums the multiplier outputs to provide a sum output. The tap weight shifter then circularly shifts the tap weights and another multiply-add operation occurs. Several shift/multiply/add cycles may occur before data is again shifted into the at least two multiple stage shift registers, and another multiply-add operation occurs.

Abstract: A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at a time, and wherein the clock switching circuitry for switching from a currently selected clock to an inactive clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit includes at least three sets of clock drivers, wherein each set is comprised of two drivers and separate clock drivers are each associated with the output clock, the currently selected clock and the clock to next be selected, respectively. An edge detector turns on these clock drivers in response to a clock select signal, and a set of synchronizers receive and synchronize the clock select signal first with the output clock and then with the currently selected clock and the clock to next be selected, respectively.

Abstract: A method and apparatus are disclosed for improving the operation of an analog-to-digital converter (“ADC”). A separate “clean” oscillator clock is to be used in combination with a “noisy” ADC clock being regulated by a phase-locked-loop (PLL) circuit. The “noisy” ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., “clean”) frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.

Abstract: An unsigned integer comparator for use when comparing an n-bit received signal (such as an address) with an n-bit known signal ("comparison address"). The first stage of the comparator may be configured in advance, since the values of both a "comparison signal" and a "select signal" are known a priori. When the "current signal" arrives, the bits of this signal are then compared against the associated bits of the comparison signal. Subsequent stages of the comparator perform comparison operations of increasing length, dependent upon the outcome of the previous stage (i.e., a first set of 2-bit comparisons, then 4-bit, 8-bit, etc.), until the entire n-bit integers are ultimately compared and a final output is generated.

Abstract: A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set.

Abstract: An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

Abstract: There is disclosed, a high speed comparator with bit-wise masking takes advantage of early availability of the reference word and mask word to generate conditional select signals, thereby minimizing the time required to generate a comparator output once the input word to be compared is available.

Abstract: An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage.