Patents by Inventor Jiancheng Zhang

Jiancheng Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7358711
    Abstract: A digital controller for controlling a regulated output of an output regulator. The output regulator responsive to a pulse width signal for controlling the transfer of energy between an input source and the regulated output. The digital controller including a duty cycle estimator to determine a nominal duty cycle. An adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. The pulse width signal being a function of the adjusted duty cycle.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: April 15, 2008
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20080030182
    Abstract: A digital controller that controls an output regulator includes controller sub-blocks that perform sub-functions of the digital controller, wherein at least one of the controller sub-blocks includes at least one of a delay line and a first comparator. A controller monitors output power states of the output regulator and controls flow of power to the at least one of the controller sub-blocks of the digital controller to reduce power consumption of the digital controller during selected ones of the output power states of the output regulator.
    Type: Application
    Filed: September 28, 2007
    Publication date: February 7, 2008
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20080030176
    Abstract: A method of controlling deadtime between power switches in an output regulator includes providing at least two power switches having a common node, wherein at least one of the two power switches is a conducting switch and a remainder of the two power switches is a free-wheeling switch, switching one of the conducting switch and the free-wheeling switch from an on-state to an off-state, during a transition from the on-state to the off-state, monitoring a current flowing through one of the conducting switch and the free-wheeling switch, comparing the current to a reference level, and delaying for a predetermined time period, then changing the operating state of the other of the conducting switch and the freewheeling switch from an off-state to an on-state.
    Type: Application
    Filed: September 28, 2007
    Publication date: February 7, 2008
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 7053594
    Abstract: A duty cycle limiter for limiting a transfer of energy between an input source and a regulated output of an output regulator. The output regulator having a regulator characteristic and a computed duty cycle for controlling the transfer of energy between the input source and the regulated output. The duty cycle limiter including a digital controller to generate a reference level and to compare the regulator characteristic of the output regulator to the reference level to determine a maximum duty cycle. The digital controller to control the reference level at a frequency at least equal to a switching frequency of the output regulator. The digital controller to limit the computed duty cycle to the maximum duty cycle.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: May 30, 2006
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 7042202
    Abstract: A digital controller for controlling an output regulator. The digital controller having sub-blocks for providing functions to control the output regulator. An energy saving discontinuous mode (ESDM) controller to monitor a sense point of the output regulator. The sense point to indicate a power state of the output regulator and the ESDM controller to control a flow of power to the sub-blocks to control power consumption of the digital controller as a function of the power state of the output regulator.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: May 9, 2006
    Assignee: Marvell World Trade LTD
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 7023192
    Abstract: An output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage. An output filter to filter the power output to generate the regulated output. An output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the power stage.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: April 4, 2006
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 7023194
    Abstract: A band gap voltage reference circuit includes a high accuracy band gap (BG) circuit that generates a BG voltage potential VbgH. A low accuracy BG circuit includes a variable resistance and outputs a BG voltage potential VbgL that is related to a value of the variable resistance. A calibration circuit communicates with the high and low accuracy BG circuits, adjusts the variable resistance based on a difference between the BG voltage potential VbgH and the BG voltage potential VbgL, and shuts down the high accuracy BG circuit when the BG voltage potential VbgL is approximately equal to the BG voltage potential VbgH.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 4, 2006
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Jiancheng Zhang
  • Patent number: 7009372
    Abstract: A control system to control an output regulator. The output regulator to convert an input voltage to a regulated output. The output regulator including a power stage to generate a power output from the input voltage and an output filter to filter the power output to generate the regulated output. A digital controller, responsive to a sense signal corresponding to the regulated output, to generate a drive signal to control the power stage.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 7, 2006
    Assignee: Marvell World Trade LTD
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20060022657
    Abstract: A digital controller for controlling a regulated output of an output regulator. The output regulator responsive to a pulse width signal for controlling the transfer of energy between an input source and the regulated output. The digital controller including a duty cycle estimator to determine a nominal duty cycle. An adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. The pulse width signal being a function of the adjusted duty cycle.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 2, 2006
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6979988
    Abstract: A duty cycle estimator for determining a nominal duty cycle of an output regulator. The duty cycle estimator having at least two modes and including at least a mode one estimator and a mode two estimator. The mode one estimator to determine the nominal duty cycle as a function of prior duty cycles. The mode two estimator to determine the nominal duty cycle as a function of accumulated error. A mode selector, based on a mode selection criteria, to select a one of the at least two modes to generate the nominal duty cycle.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: December 27, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6977490
    Abstract: A voltage regulator apparatus includes an error amplifier that amplifies a voltage difference between a reference and a sampled output voltage of the voltage regulator apparatus. A driver amplifier has an input that is responsive to the amplified voltage difference to produce a gate driving voltage at its output. An output transistor having a drain, a gate, and a source is also included. The gate is responsive to the gate driving voltage to produce a regulated output voltage at the source. To stabilize the voltage regulator apparatus, a Miller compensation capacitor is provided to feed a sample of the regulated output voltage back to the input of the driver amplifier; and additionally, an Ahuja compensation circuit is provided to feed back a portion of the regulated output voltage back to the input of the driver amplifier.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 20, 2005
    Assignee: Marvell International Ltd.
    Inventors: Hong Zhang, Jiancheng Zhang, Sehat Sutardja
  • Patent number: 6977492
    Abstract: A control system for controlling an output regulator having a regulated output. The control system including an output sensor to generate a digital sense signal to indicate within which of at least three reference ranges the regulated output is included. Each of the at least three reference ranges including a plurality of possible values of the regulated output. A digital controller, responsive to the digital sense signal, to generate a drive signal to control the regulated output.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 20, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6933711
    Abstract: A circuit for generating a feedback signal corresponding to a regulated output. The circuit including a reference generator to generate at least two reference levels, the reference levels to define at least three reference ranges. A comparator to compare the regulated output to the at least three reference ranges. The comparator to generate a digital signal to indicate within which of the at least three reference ranges the regulated output is included.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 23, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20050156581
    Abstract: A power array for converting an input voltage to a chopped output used in an output regulator that converts the chopped output to a regulated output. The power array including a switch array, responsive to independent drive signals, to convert the input voltage to the chopped output at a switching frequency. The switch array including at least two power switches. A switch controller to generate the independent drive signals as a function of a duty cycle signal. The switch controller to operate at a sampling frequency, the sampling frequency being greater than the switching frequency. The switch controller to control the independent drive signals at a drive frequency greater than the switching frequency.
    Type: Application
    Filed: March 15, 2005
    Publication date: July 21, 2005
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Patent number: 6894465
    Abstract: A power array for converting an input voltage to a chopped output used in an output regulator that converts the chopped output to a regulated output. The power array including a switch array, responsive to independent drive signals, to convert the input voltage to the chopped output at a switching frequency. The switch array including at least two power switches. A switch controller to generate the independent drive signals as a function of a duty cycle signal. The switch controller to operate at a sampling frequency, the sampling frequency being greater than the switching frequency. The switch controller to control the independent drive signals at a drive frequency greater than the switching frequency.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: May 17, 2005
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20050030770
    Abstract: Systems and techniques for efficient power regulators with improved reliability. A power regulator may include a first driver including a first switch and a second switch, where a power dissipation of the first switch is less than a power dissipation of the second switch. The power regulator may include a second driver. The first and second switches may be implemented as transistors, which may have different on-state breakdown voltages and/or on-state drain source resistances.
    Type: Application
    Filed: December 22, 2003
    Publication date: February 10, 2005
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Jiancheng Zhang, Sofjan Goenawan
  • Patent number: 6844711
    Abstract: A band gap voltage reference circuit includes a high power band gap (BG) circuit that generates a BG voltage potential VbgH. A low power BG circuit includes a variable resistance and outputs a BG voltage potential VbgL that is related to a value of the variable resistance. The low power BG circuit has a lower accuracy than the high power BG circuit. A calibration circuit communicates with the high and low power BG circuits, adjusts the variable resistance based on a difference between the BG voltage potential VbgH and the BG voltage potential VbgL, and shuts down the high power BG circuit when the BG voltage potential VbgL is approximately equal to the BG voltage potential VbgH.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 18, 2005
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Jiancheng Zhang
  • Publication number: 20040239300
    Abstract: A digital controller for controlling an output regulator. The digital controller having sub-blocks for providing functions to control the output regulator. An energy saving discontinuous mode (ESDM) controller to monitor a sense point of the output regulator. The sense point to indicate a power state of the output regulator and the ESDM controller to control a flow of power to the sub-blocks to control power consumption of the digital controller as a function of the power state of the output regulator.
    Type: Application
    Filed: April 19, 2004
    Publication date: December 2, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040196015
    Abstract: A duty cycle estimator for determining a nominal duty cycle of an output regulator. The duty cycle estimator having at least two modes and including at least a mode one estimator and a mode two estimator. The mode one estimator to determine the nominal duty cycle as a function of prior duty cycles. The mode two estimator to determine the nominal duty cycle as a function of accumulated error. A mode selector, based on a mode selection criteria, to select a one of the at least two modes to generate the nominal duty cycle.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang
  • Publication number: 20040196016
    Abstract: A digital controller for controlling a regulated output of an output regulator. The output regulator responsive to a pulse width signal for controlling the transfer of energy between an input source and the regulated output. The digital controller including a duty cycle estimator to determine a nominal duty cycle. An adjust determiner to determine an adjustment value to combine with the nominal duty cycle to generate an adjusted duty cycle. The pulse width signal being a function of the adjusted duty cycle.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Applicant: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Runsheng He, Jiancheng Zhang