Patents by Inventor Jiangyuan Zhang
Jiangyuan Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8674490Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.Type: GrantFiled: February 24, 2011Date of Patent: March 18, 2014Assignee: Fairchild Semiconductor CorporatioInventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
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Patent number: 8399997Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.Type: GrantFiled: June 10, 2011Date of Patent: March 19, 2013Assignee: Shanghai Kalhong Electronic Company LimitedInventors: Jiangyuan Zhang, Elite Lee, Dana Liu
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Patent number: 8367481Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.Type: GrantFiled: February 15, 2012Date of Patent: February 5, 2013Assignee: Fairchild Semiconductor CorporationInventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Luke Huiyong Chung
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Publication number: 20130005083Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.Type: ApplicationFiled: February 15, 2012Publication date: January 3, 2013Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, Jung Tae Lee, Luke Huiyong Chung
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Publication number: 20120315727Abstract: In one embodiment, a method for manufacturing a power semiconductor package is provided. The method includes attaching a plurality of solders balls onto a power semiconductor device. The plurality of solder balls are attached onto a lead frame using a flip bond processing step. The flip bond processing step bonds the semiconductor device to the lead frame and interconnects the lead frame to the semiconductor device in a single processing step. The semiconductor device, plurality of solder balls, and the lead frame are molded to form the power semiconductor package, wherein semiconductor device is exposed on a first side of the semiconductor package.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: SHANGHAI KAIHONG ELECTRONIC COMPANY LIMITEDInventors: Jiangyuan Zhang, Elite Lee, Dana Liu
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Publication number: 20120313232Abstract: In one embodiment, a method includes attaching a film to cover a first portion of a first semiconductor die. The first semiconductor die is attached, using the tape, to a lead frame using a first bonding method. The first bonding method places the film between the lead frame and the semiconductor die. A second semiconductor die is attached to the lead frame using a second bonding method. The second bonding method bonds the lead frame and the semiconductor die. The first semiconductor device and the second semiconductor device are encapsulated into a semiconductor package.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: SHANGHAI KAIHONG ELECTRONIC COMPANY LIMITEDInventors: Jiangyuan Zhang, Elite Lee, Dana Liu
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Publication number: 20120149149Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, Jung Tae Lee, Luke Huiyong Chung
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Patent number: 8138585Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.Type: GrantFiled: May 28, 2008Date of Patent: March 20, 2012Assignee: Fairchild Semiconductor CorporationInventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Huiyong Luke Chung
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Publication number: 20110140255Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.Type: ApplicationFiled: February 24, 2011Publication date: June 16, 2011Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
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Patent number: 7915721Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.Type: GrantFiled: March 12, 2008Date of Patent: March 29, 2011Assignee: Fairchild Semiconductor CorporationInventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian
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Publication number: 20090294936Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Inventors: Yong Liu, Qiuxiao Qian, JiangYuan Zhang, Mike Speed, JungTae Lee, Huiyong Luke Chung
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Publication number: 20090230518Abstract: A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.Type: ApplicationFiled: March 12, 2008Publication date: September 17, 2009Inventors: Yong Liu, Jiangyuan Zhang, Qiuxiao Qian