Patents by Inventor Jian Guo Ma
Jian Guo Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373876Abstract: A fully integrated silicon-based bandpass filter which lends itself to applications in the gigahertz region is disclosed. The bandpass filter is fabricated on an integrated circuit and operates as a microwave/millimeter-wave filtering circuit. In accordance with one aspect, the bandpass filter includes a first set and a second set of filter coupled elements, a three-port “T” transmission line junction and a perturbing element. The three-port “T” transmission line junction has a first port coupled to a first end of a first one of the first set of filter coupled elements and a second port coupled to a first end of a first one of the second set of filter coupled elements. The perturbing element is coupled to a third port of the three-port “T” transmission line junction. A second one of the first set of filter coupled elements includes an input transmission line and has a first end thereof coupled to an input port and an opposite end thereof having an open end.Type: GrantFiled: October 27, 2011Date of Patent: June 21, 2016Assignee: Nanyang Technological UniversityInventors: Kai Xue Ma, Kok Meng Lim, Kiat Seng Yeo, Jian-guo Ma
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Patent number: 9083437Abstract: In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal.Type: GrantFiled: August 24, 2010Date of Patent: July 14, 2015Assignee: Agency for Science, Technology and ResearchInventors: Kiat Seng Yeo, Jian Guo Ma
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Publication number: 20140035703Abstract: A fully integrated silicon-based bandpass filter which lends itself to applications in the gigahertz region is disclosed. The bandpass filter is fabricated on an integrated circuit and operates as a microwave/millimeter-wave filtering circuit. In accordance with one aspect, the bandpass filter includes a first set and a second set of filter coupled elements, a three-port “T” transmission line junction and a perturbing element. The three-port “T” transmission line junction has a first port coupled to a first end of a first one of the first set of filter coupled elements and a second port coupled to a first end of a first one of the second set of filter coupled elements. The perturbing element is coupled to a third port of the three-port “T” transmission line junction. A second one of the first set of filter coupled elements includes an input transmission line and has a first end thereof coupled to an input port and an opposite end thereof having an open end.Type: ApplicationFiled: October 27, 2011Publication date: February 6, 2014Applicant: NANYANG TECHNOLOGICAL UNIVERSITYInventors: Kai Xue Ma, Kok Meng Lim, Kiat Seng Yeo, Jian-guo Ma
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Publication number: 20120274367Abstract: In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal.Type: ApplicationFiled: August 24, 2010Publication date: November 1, 2012Inventors: Kiat Seng Yeo, Jian Guo Ma
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Patent number: 6803848Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: GrantFiled: October 15, 2002Date of Patent: October 12, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6800533Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.Type: GrantFiled: March 6, 2000Date of Patent: October 5, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6535098Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: GrantFiled: March 6, 2000Date of Patent: March 18, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Publication number: 20030043010Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: ApplicationFiled: October 15, 2002Publication date: March 6, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6521939Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.Type: GrantFiled: September 29, 2000Date of Patent: February 18, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat-Seng Yeo, Chun Qi Geng, Kok-Wai Chew, Manh-Anh Do, Jian Guo Ma
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Publication number: 20030013264Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.Type: ApplicationFiled: September 3, 2002Publication date: January 16, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6292060Abstract: In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.Type: GrantFiled: September 13, 1999Date of Patent: September 18, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat-Seng Yeo, Kok Lim Chan, Manh Anh Do, Jian Guo Ma, Johnny Kok Wai Chew