Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Abstract: Provided an intermittent characteristic-based demand-side resource coordination control method and system. The method includes: receiving a control request, where the control request is used for requesting control of demand-side resources having an intermittent characteristic; determining a target total control quantity of demand-side resources; determining a coordination strategy of multiple demand-side resources and an action quantity of each of the multiple demand-side resources; and performing coordinated control on the multiple demand-side resources based on the target total control quantity of demand-side resources, the coordination strategy, and the action quantity of each of the multiple demand-side resources.

Abstract: A metal-based dissolvable ball seat comprises a mandrel, a tail base, a sliding body, a slip and a sealing ring. The mandrel can be disengaged from the tail base under predefined shearing force. The sliding body is disposed to sleeve the mandrel and located above the tail base; the slip is disposed outside the mandrel and slidably abutted against the tail base and the sliding body respectively; the slip and the sliding body are slidably abutted against each other through a first conical surface structure, and/or the slip and the tail base are slidably abutted against each other through a second conical surface structure; the sealing ring is movable along axial direction of the mandrel together with the slip; when the sliding body and the tail base are approaching each other, the slip opens up and the sealing ring expands outward. A setting system and a setting method are provided.

Abstract: In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

Abstract: Embodiments of the present disclosure disclose a method and an apparatus for handling network congestion, and a system. The method includes: obtaining a transmitted data volume of a flow, and identifying a predictable flow and a non-predictable flow in the flow; collecting statistics about total data transmission volumes of the predictable flow and the non-predictable flow; obtaining a congestion transmission model of the predictable flow, and solving the congestion transmission model to obtain a scheduling policy for the predictable flow; and allocating bandwidths to the predictable flow and the non-predictable flow to obtain a bandwidth allocation result, and sending the bandwidth allocation result and the scheduling policy to the host, so that the host executes the scheduling policy in a scheduling period. This can prevent congestion in advance and reduce a delay of a delay-sensitive flow, and is applicable to a large data center.

Abstract: The present invention provides a multi-resource scheduling method responding to uncertain demands in a cloud scheduler, where two computation formulas for fairness and efficiency are used as cost functions in an optimization problem. For some change sets with uncertain resource demands, a robust counterpart of an original non-linear optimization problem is computationally tractable. Therefore, the present invention models features of these sets with uncertain resource demands, i.e., establishes an ellipsoidal uncertainty model. In this model, each coefficient vector is put into a hyper-ellipsoidal space and used as a metric to measure an uncertainty degree. With the ellipsoidal uncertainty model, a non-linear optimization problem is solved and a resource allocation solution that can respond to dynamically changing demands can be obtained.

Abstract: A metal-based dissolvable ball seat comprises a mandrel, a tail base, a sliding body, a slip and a sealing ring. The mandrel can be disengaged from the tail base under predefined shearing force. The sliding body is disposed to sleeve the mandrel and located above the tail base; the slip is disposed outside the mandrel and slidably abutted against the tail base and the sliding body respectively; the slip and the sliding body are slidably abutted against each other through a first conical surface structure, and/or the slip and the tail base are slidably abutted against each other through a second conical surface structure; the sealing ring is movable along axial direction of the mandrel together with the slip; when the sliding body and the tail base are approaching each other, the slip opens up and the sealing ring expands outward. A setting system and a setting method are provided.

Abstract: The present invention provides a multi-resource scheduling method responding to uncertain demands in a cloud scheduler, where two computation formulas for fairness and efficiency are used as cost functions in an optimization problem. For some change sets with uncertain resource demands, a robust counterpart of an original non-linear optimization problem is computationally tractable. Therefore, the present invention models features of these sets with uncertain resource demands, i.e., establishes an ellipsoidal uncertainty model. In this model, each coefficient vector is put into a hyper-ellipsoidal space and used as a metric to measure an uncertainty degree. With the ellipsoidal uncertainty model, a non-linear optimization problem is solved and a resource allocation solution that can respond to dynamically changing demands can be obtained.

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Abstract: A Demand Response (DR) physical potential evaluation method for a feeder line is provided, which includes that: a load curve of a part to be identified in a load curve of a feeder line to be evaluated is acquired; a load database is created on the basis of a historical load curve of loads of predefined types; load types and total number of the loads to be identified are determined on the basis of the load curve of the part to be identified and the load database; a physical potential of the loads of each of the types is acquired according to the load types of the loads to be identified; and an overall aggregated physical potential of the loads to be identified is obtained according to the physical potential of the loads of each of the types and a number of the loads of each of the types.

Abstract: The present invention relates to Data Center Network (DCN) flow scheduling scheme. It provides a dynamic scheduling algorithm and a hybrid of centralized and decentralized scheduling system to improve the performance of DCN and data parallel application. The scheduling system uses a central controller to collect the real-time bandwidth of each node, and schedule the priority as well as transmission rate of each network flow set combined by application context (Coflow [1]). The centralized scheduling avoids a sophisticated system design and hardware (switch) modification to comparing with full decentralized solutions. The combination of centralization and decentralization decreases the average completion time of Coflows, and eventually improve the performance of data parallel applications.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: The present disclosure provides a virtualization method for a device MMU, including: multiplexing a client MMU as a first layer address translation: a client device page table translates a device virtual address into a client physical address; using IOMMU to construct a second layer address translation: IOMMU translates the client physical address into a host physical address through a TO page table of a corresponding device in IOMMU. The virtualization method for a device MMU proposed by the present disclosure can efficiently virtualize the device MMU; successfully combines IOMMU into Mediated Pass-Through, and uses the system IOMMU to perform the second layer address translation, such that the complicated and inefficient Shadow Page Table is abandoned; not only improves the performance of the device MMU under virtualization, but also is simple to implement and completely transparent to the client, and is a universal and efficient solution.

Abstract: Embodiments of the present disclosure disclose a method and an apparatus for handling network congestion, and a system. The method includes: obtaining a transmitted data volume of a flow, and identifying a predictable flow and a non-predictable flow in the flow; collecting statistics about total data transmission volumes of the predictable flow and the non-predictable flow; obtaining a congestion transmission model of the predictable flow, and solving the congestion transmission model to obtain a scheduling policy for the predictable flow; and allocating bandwidths to the predictable flow and the non-predictable flow to obtain a bandwidth allocation result, and sending the bandwidth allocation result and the scheduling policy to the host, so that the host executes the scheduling policy in a scheduling period. This can prevent congestion in advance and reduce a delay of a delay-sensitive flow, and is applicable to a large data center.

Abstract: A magnetic random access memory (MRAM) array is described. The MRAM array includes bit cells, and each bit cell includes a magnetic tunnel junction (MTJ). The MTJ include a barrier layer between a free layer and a pinned layer. In addition the bit cells are shorted together. The MRAM array also includes wordline (WL) devices, each coupled to one of the bit cells. The MRAM array further includes a tristate bit line (BL) driver coupled to each of the bit cells. The MRAM array also includes a tristate source line (SL) driver coupled to each of the bit cells via the WL devices.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance are disclosed. Added passive resistance can enhance imbalance between transistors in the SRAM bit cell for improved PUF output reproducibility. Enhancing transistor imbalance can more fully skew the SRAM bit cell for increased PUF output reproducibility while still achieving the benefits of output randomness. In one exemplary aspect, added passive resistances in the SRAM bit cell are coupled to a drain of one or more pull-down N-type FETs (NFETs)) in one or more cross-coupled inverters in the SRAM bit cell to enhance imbalance between the inverters. Enhanced imbalance between the inverters increases sensitivity in the output voltage of the SRAM bit cell for a given change in input voltage resulting in greater skew of the SRAM bit cell for increased reproducibility.

Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.

Abstract: Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.

Abstract: The present invention relates to Data Center Network (DCN) flow scheduling scheme. It provides a dynamic scheduling algorithm and a hybrid of centralized and decentralized scheduling system to improve the performance of DCN and data parallel application. The scheduling system uses a central controller to collect the real-time bandwidth of each node, and schedule the priority as well as transmission rate of each network flow set combined by application context (Coflow [1]). The centralized scheduling avoids a sophisticated system design and hardware (switch) modification to comparing with full decentralized solutions. The combination of centralization and decentralization decreases the average completion time of Coflows, and eventually improve the performance of data parallel applications.