Patents by Inventor Jianhui Ye
Jianhui Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11423638Abstract: An optical sensor module for sensing a face of a person for user identification and authentication, where a face illumination module is provided to use an array of face illumination light sources arranged in a regular array pattern to produce illumination light which may be invisible light such as infrared light and an optical diffraction element that is located to receive illumination light beams from the face illumination light sources and to transfer each illumination light beam from each face illumination light source in the array into a patterned light beam containing illumination light spots.Type: GrantFiled: March 24, 2020Date of Patent: August 23, 2022Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.Inventors: Jianhui Ye, Bo Pi
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Publication number: 20200364489Abstract: An optical sensor module for sensing a face of a person for user identification and authentication, where a face illumination module is provided to use an array of face illumination light sources arranged in a regular array pattern to produce illumination light which may be invisible light such as infrared light and an optical diffraction element that is located to receive illumination light beams from the face illumination light sources and to transfer each illumination light beam from each face illumination light source in the array into a patterned light beam containing illumination light spots.Type: ApplicationFiled: March 24, 2020Publication date: November 19, 2020Inventors: Jianhui YE, Bo PI
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Patent number: 8354347Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: GrantFiled: December 11, 2007Date of Patent: January 15, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Chun Hui Low, Chim Seng Seet, Mei Sheng Zhou, Liang Choo Hsia
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Patent number: 7960283Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.Type: GrantFiled: June 28, 2010Date of Patent: June 14, 2011Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jeff Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Hai Cong, Hui Peng Koh, Mei Sheng Zhou, Liang Choo Hsia
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Publication number: 20100267236Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.Type: ApplicationFiled: June 28, 2010Publication date: October 21, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Hai CONG, Hui Peng KOH, Mei Sheng ZHOU, Liang Choo HSIA
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Patent number: 7745320Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.Type: GrantFiled: May 21, 2008Date of Patent: June 29, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jeff Jianhui Ye, Huang Liu, Alex K H See, Wei Lu, Hai Cong, Hui Peng Koh, Mei Sheng Zhou, Liang Choo Hsia
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Publication number: 20090289309Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Hai CONG, Hui Peng KOH, Mei Sheng ZHOU, Liang Choo HSIA
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Publication number: 20090146296Abstract: A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.Type: ApplicationFiled: December 11, 2007Publication date: June 11, 2009Applicant: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jianhui YE, Huang LIU, Alex KH SEE, Wei LU, Chun Hui LOW, Chim Seng SEET, Mei Sheng ZHOU, Liang Choo HSIA
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Publication number: 20070066047Abstract: A method for forming an opening on a material layer is provided. First, a dielectric layer is formed on the material layer. Then, a metallic hard mask layer and a cap layer are sequentially formed on the dielectric layer. Thereafter, a patterned photoresist layer is formed on the cap layer. The patterned photoresist layer exposes a portion of the surface of the cap layer. After that, a first etching operation is carried out using the patterned photoresist layer as a mask to remove a portion of the cap layer and the metallic hard mask layer until the surface of the dielectric layer is exposed. Then, the photoresist layer is removed. A second etching operation is carried out using the cap layer and the metallic hard mask layer as a mask to remove a portion of the dielectric layer and form an opening.Type: ApplicationFiled: September 18, 2005Publication date: March 22, 2007Inventors: Jianhui Ye, Kai Hung Alex See, Tien-Cheng Lan, Meisheng Zhou
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Patent number: 6638365Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.Type: GrantFiled: October 9, 2001Date of Patent: October 28, 2003Assignees: Chartered Semiconductor Manufacturing Ltd., Institute of Materials Research and EngineeringInventors: Jianhui Ye, Simon Chooi, Alex See
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Publication number: 20030069151Abstract: A method of preparing a silicon surface for a subsequent processing said such as thermal oxidation, or metal silicide formation, via use of a novel wet chemical clean procedure, has been developed. The novel wet chemical clean procedure is comprised of three specific stages, with the first stage featuring the removal of organic contaminants and the growth of a native oxide layer on the silicon surface. A second stage features removal of the native oxide layer and removal of metallic contaminants from the silicon surface, while the third stage is used to dry the silicon surface. The novel wet chemical clean procedure is performed in less time, and using less chemicals, then counterpart wet chemical cleans also used for the preparation of silicon surfaces for subsequent processing steps.Type: ApplicationFiled: October 9, 2001Publication date: April 10, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Jianhui Ye, Simon Chooi, Alex See
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Patent number: 6063547Abstract: A method of patterning conductive lines using a bottom anti-reflective coating (BARC) composed of Poly-p-phenylene sulfide (PPS) film 30 formed using a Physical Vapor Deposition (PVD) process. The PPS BARC 30 is easy to remove and has superior planarization. The method comprises:a) forming conductive layer 26 over a semiconductor structure 10;b) forming a Poly-p-phenylene sulfide (PPS) layer 30 over said conductive layer using a Physical Vapor Deposition (PVD) process;c) forming a photoresist pattern 34 over said Poly-p-phenylene sulfide (PPS) layer 30; said Poly-p-phenylene sulfide (PPS) layer acting as a bottom Anti-reflective coating (BARC);d) etching said conductive layer 26 using said photoresist pattern 34 and as a mask forming a conductive pattern;e) removing said photoresist pattern 34;f) removing said Poly-p-phenylene sulfide (PPS) layer by heating and vaporizing said Poly-p-phenylene sulfide (PPS) layer.Type: GrantFiled: June 11, 1998Date of Patent: May 16, 2000Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Jianhui Ye, Mei Sheng Zhou