Patents by Inventor Jiani Zhang
Jiani Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959805Abstract: The system is configured to locate, track and/or analyze activities of living beings in an environment. The system does not require the input of personal biometric data. The sensor system detects infrared (IR) energy from a living being moving in an environment, determines a temperature of the living being based on IR energy data of the IR energy, projects the temperature onto a grid having sequential pixels, determines serial changes of the temperature in the sequential pixels and determines a trajectory of the living being based on the serial changes of the temperature in the sequential pixels.Type: GrantFiled: April 3, 2023Date of Patent: April 16, 2024Assignee: BUTLR TECHNOLOGIES, INC.Inventors: Honghao Deng, Jiani Zeng, Ziran Zhang, Yan Zhang
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Patent number: 11899896Abstract: Disclosed are a flexible screen terminal device and a display method therefor, and a non-transitory computer-readable storage medium. The display method may include: determining a folding boundary line corresponding to a folding operation in response to a detection of the folding operation corresponding to the flexible screen terminal; and performing a split-screen display operation based on the folding boundary line and a preset display rule of the flexible screen terminal device.Type: GrantFiled: July 8, 2020Date of Patent: February 13, 2024Assignee: ZTE CORPORATIONInventors: Xipeng Li, Song Dang, Yi Wang, Xiaohong Chai, Jiani Zhang, Ningyuan Wu
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Publication number: 20220206643Abstract: Disclosed are a flexible screen terminal device and a display method therefor, and a non-transitory computer-readable storage medium. The display method may include: determining a folding boundary line corresponding to a folding operation in response to a detection of the folding operation corresponding to the flexible screen terminal; and performing a split-screen display operation based on the folding boundary line and a preset display rule of the flexible screen terminal device.Type: ApplicationFiled: July 8, 2020Publication date: June 30, 2022Inventors: Xipeng LI, Song DANG, Yi WANG, Xiaohong CHAI, Jiani ZHANG, Ningyuan Wu
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Publication number: 20220191170Abstract: Provided are an Access Point Name (APN) configuration method and apparatus, and a readable storage medium. The APN configuration method includes: determining, by a terminal, an APN category of a candidate APN, wherein the APN category includes an APN used in a 5G network or an APN used in a non-5G network; determining, by the terminal, a network mode of the terminal according to a configuration parameter of the terminal, wherein the network mode includes a network mode supporting the 5G network or a network mode not supporting the 5G network; and determining, by the terminal, according to whether the APN category matches the network mode, whether to execute network access based on the candidate APN.Type: ApplicationFiled: July 22, 2020Publication date: June 16, 2022Inventors: Xipeng LI, Song DANG, Zitao XUE, Jiani ZHANG
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Patent number: 11194536Abstract: Disclosed is an image processing method. The method includes: determining that an original image is to be displayed on a dividing line between two display screens; acquiring a complete display picture of the original image, and calculating distances from boundaries of the original image to the dividing line; and adjusting a display position of the original image on the two display screens according to the distances, and displaying the complete display picture of the original image according to the adjusted display position. Further disclosed are an image processing apparatus, a storage medium and a processor.Type: GrantFiled: July 9, 2018Date of Patent: December 7, 2021Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTDInventors: Dongmei Liu, Fengpeng Liu, Song Dang, Xipeng Li, Jiani Zhang
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Patent number: 11188616Abstract: An illustrative embodiment includes a method for solving a dynamical system. The method comprises: obtaining multidimensional snapshots representing respective discrete solutions of the dynamical system; storing the multidimensional snapshots within a snapshot tensor having an order of at least three; generating a basis for at least a subspace of a state space of the dynamical system at least in part by performing a decomposition of the snapshot tensor; deriving a reduced order model at least in part by using the basis to project the dynamical system from the state space onto the subspace; and solving the reduced order model of the dynamical system.Type: GrantFiled: February 25, 2020Date of Patent: November 30, 2021Assignees: International Business Machines Corporation, Trustees of Tufts College, Ramot at Tel Aviv University Ltd.Inventors: Lior Horesh, Misha Elena Kilmer, Haim Avron, Jiani Zhang
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Publication number: 20210271730Abstract: An illustrative embodiment includes a method for solving a dynamical system. The method comprises: obtaining multidimensional snapshots representing respective discrete solutions of the dynamical system; storing the multidimensional snapshots within a snapshot tensor having an order of at least three; generating a basis for at least a subspace of a state space of the dynamical system at least in part by performing a decomposition of the snapshot tensor; deriving a reduced order model at least in part by using the basis to project the dynamical system from the state space onto the subspace; and solving the reduced order model of the dynamical system.Type: ApplicationFiled: February 25, 2020Publication date: September 2, 2021Inventors: Lior Horesh, Misha Elena Kilmer, Haim Avron, Jiani Zhang
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Publication number: 20200272399Abstract: Disclosed is an image processing method. The method includes: determining that an original image is to be displayed on a dividing line between two display screens; acquiring a complete display picture of the original image, and calculating distances from boundaries of the original image to the dividing line; and adjusting a display position of the original image on the two display screens according to the distances, and displaying the complete display picture of the original image according to the adjusted display position. Further disclosed are an image processing apparatus, a storage medium and a processor.Type: ApplicationFiled: July 9, 2018Publication date: August 27, 2020Inventors: Dongmei LIU, Fengpeng LIU, Song DANG, Xipeng LI, Jiani ZHANG
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Patent number: 9338168Abstract: The present document provides a method and apparatus for controlling digital living network alliance contents. One Media Access Control (MAC) recording unit is extended at the Digital Living Network Alliance (DLNA) device side for recording which MAC addresses are permitted to access or use the service of the DLNA device or prohibited from accessing or using the service of the DLNA device; one service control program is extended at the DLNA device side, and when there is another DLNA device transmitting a request to the DLNA device, the MAC address of the DLNA device is compared with the MAC address recorded by the MAC recording unit; and if the MAC address of the DLNA device is in the permission list or the MAC address of the DLNA device is not in the prohibition list, then the request will be permitted; otherwise the request will be rejected.Type: GrantFiled: November 29, 2011Date of Patent: May 10, 2016Assignee: ZTE CorporationInventors: Jiani Zhang, Huibin Li
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Publication number: 20140215579Abstract: The present document provides a method and apparatus for controlling digital living network alliance contents. One Media Access Control (MAC) recording unit is extended at the Digital Living Network Alliance (DLNA) device side for recording which MAC addresses are permitted to access or use the service of the DLNA device or prohibited from accessing or using the service of the DLNA device; one service control program is extended at the DLNA device side, and when there is another DLNA device transmitting a request to the DLNA device, the MAC address of the DLNA device is compared with the MAC address recorded by the MAC recording unit; and if the MAC address of the DLNA device is in the permission list or the MAC address of the DLNA device is not in the prohibition list, then the request will be permitted; otherwise the request will be rejected.Type: ApplicationFiled: November 29, 2011Publication date: July 31, 2014Applicant: ZTE CORPORATIONInventors: Jiani Zhang, Huibin Li
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Publication number: 20140024337Abstract: The present disclosure discloses a method for calculating a call expense of a terminal, including that: after receiving a call attribute, a cost calculating module reads a billing rule and an account balance in a cost file, calculates a call expense and a current account balance, and then updates the account balance in the cost file; and the billing rule and the account balance in the cost file are also updated in time through an Over-The-Air (OTA) short message. The present disclosure also disclosures a system for calculating a call expense of a terminal. With the present disclosure, timely and accurate call expense information can be provided for a subscriber.Type: ApplicationFiled: March 15, 2012Publication date: January 23, 2014Applicant: ZTE CORPORATIONInventors: Lijun Fang, Jiani Zhang, Hailong Wen
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Patent number: 7948035Abstract: The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further includes a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.Type: GrantFiled: February 20, 2008Date of Patent: May 24, 2011Assignee: Spansion LLCInventors: Nian Yang, Joon-Heong Ong, Jiani Zhang
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Patent number: 7808827Abstract: Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.Type: GrantFiled: November 6, 2007Date of Patent: October 5, 2010Assignee: Spansion LLCInventors: Aaron Lee, Nian Yang, Jiani Zhang
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Patent number: 7613042Abstract: Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods are disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.Type: GrantFiled: November 5, 2007Date of Patent: November 3, 2009Assignee: Spansion LLCInventors: Jiani Zhang, Nian Yang, Aaron Lee
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Publication number: 20090206386Abstract: One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.Type: ApplicationFiled: February 20, 2008Publication date: August 20, 2009Applicant: Spansion LLCInventors: Nian Yang, Joon-Heong Ong, Jiani Zhang
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Publication number: 20090116289Abstract: Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods arc disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.Type: ApplicationFiled: November 5, 2007Publication date: May 7, 2009Inventors: Jiani Zhang, Nian Yang, Aaron Lee
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Publication number: 20090119447Abstract: Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.Type: ApplicationFiled: November 6, 2007Publication date: May 7, 2009Applicant: SPANSION LLCInventors: Aaron Lee, Nian Yang, Jiani Zhang