Patents by Inventor Jianjian SHENG
Jianjian SHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240170957Abstract: A method for wafer-level adjustment of protection circuits of electronic devices and a wafer for facilitating the same are provided. The method comprises: fabricating an adjustable terminal protection circuit for each of the electronic devices in the wafer; and adjusting each of the adjustable terminal protection circuits by cutting off one or more fuse elements in the one or more trimming circuits of the terminal protection circuit. The method provides a cost-effective approach to allow wafer-level on-chip adjustment of protection circuits for III-V compound devices in a flexible manner so as to address the issues of manufacturing process constrains under requirement of large wafer dimension.Type: ApplicationFiled: April 20, 2022Publication date: May 23, 2024Inventor: Jianjian SHENG
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Publication number: 20240096878Abstract: The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor, a first conductive terminal and a second conductive terminal disposed on a second region of the second nitride semiconductor layer, and a resistor formed in the first nitride semiconductor layer and electrically connected between the first conductive terminal and the second conductive terminal, wherein the resistor comprises at least one conductive region.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Applicant: INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.Inventors: Danfeng MAO, King Yuen WONG, Jinhan ZHANG, Xiaoyan ZHANG, Wei WANG, Jianjian SHENG
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Patent number: 11869887Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.Type: GrantFiled: December 25, 2020Date of Patent: January 9, 2024Inventors: Danfeng Mao, King Yuen Wong, Jinhan Zhang, Xiaoyan Zhang, Wei Wang, Jianjian Sheng
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Publication number: 20230352476Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first field plate, and a second field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate structure is disposed above the second nitride-based semiconductor layer. The first field plate is disposed over the gate structure and is electrically coupled with the source electrode and the drain electrode. The second field plate is disposed over the gate structure and is electrically coupled with the gate structure. The first field plate and the second field plate are parallel with each other. A top surface of the first field plate faces a bottom surface of the second field plate to overlap with each other.Type: ApplicationFiled: October 27, 2021Publication date: November 2, 2023Inventors: Xin ZHANG, Jianjian SHENG, Junyuan LV, Zhenzhe LI
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Patent number: 11764210Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).Type: GrantFiled: June 21, 2022Date of Patent: September 19, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Yaobin Guan, Jianjian Sheng
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Patent number: 11721969Abstract: An electronic device includes a first group III nitride transistor and an over current protection circuit (OCP). The OCP circuit includes an input device and a detection device. The input device is configured to receive a control signal and to generate a first voltage to a gate of the first group III nitride transistor. The detection device is configured to generate an output signal having a first logical value if a current at a drain of the first group III nitride transistor is less than a predetermined value and to generate the output signal having a second logical value if the current at the drain of the first group III nitride transistor is equal to or greater than the predetermined value, wherein the first logical value is different from the second logical value.Type: GrantFiled: May 20, 2020Date of Patent: August 8, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Jianjian Sheng, Yaobin Guan
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Patent number: 11715946Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.Type: GrantFiled: November 30, 2020Date of Patent: August 1, 2023Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.Inventors: Yaobin Guan, Jianjian Sheng, Zhenzhe Li, Junyuan Lv
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CLAMPING CIRCUIT INTEGRATED ON GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND RELATED SEMICONDUCTOR DEVICE
Publication number: 20230178541Abstract: A semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series. One end of the first transistor structures and one end of the second transistor structures are jointly electrically connected to the drain structure of the power transistor structure, and the other end of the first transistor structures and the other end of the second transistor structures are jointly electrically connected to the source structure of the power transistor structure.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventors: Yaobin GUAN, Jianjian SHENG -
Clamping circuit integrated on gallium nitride semiconductor device and related semiconductor device
Patent number: 11600610Abstract: The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series.Type: GrantFiled: April 28, 2020Date of Patent: March 7, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Yaobin Guan, Jianjian Sheng -
Publication number: 20220375928Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor; and a capacitor having a first conductive layer and a second conductive layer and disposed on a second region of the second nitride semiconductor layer. Wherein the first conductive layer of the capacitor and the first source electrode have a first material, and the second conductive layer of the capacitor and the first field plate have a second material.Type: ApplicationFiled: December 25, 2020Publication date: November 24, 2022Inventors: Danfeng MAO, King Yuen WONG, Jinhan ZHANG, Xiaoyan ZHANG, Wei WANG, Jianjian SHENG
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Publication number: 20220375927Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a nitride semiconductor layer disposed on the substrate, a first gate stack in contact with the nitride semiconductor layer, and a resistor laterally spaced apart from the first gate stack and electrically connected to first gate stack. The resistor comprises a first conductive terminal in contact with the nitride semiconductor layer, a second conductive terminal in contact with the nitride semiconductor layer; a first doped region of the nitride semiconductor layer between the first conductive terminal and the second conductive terminal; and a first conductive region of the nitride semiconductor layer in contact with the first conductive terminal and the second conductive terminal.Type: ApplicationFiled: December 25, 2020Publication date: November 24, 2022Inventors: Danfeng MAO, King Yuen WONG, Jinhan ZHANG, Xiaoyan ZHANG, Wei WANG, Jianjian SHENG
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Publication number: 20220376494Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.Type: ApplicationFiled: November 30, 2020Publication date: November 24, 2022Inventors: YAOBIN GUAN, JIANJIAN SHENG, ZHENZHE LI, JUNYUAN LV
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Publication number: 20220376490Abstract: An electronic device includes a first group III nitride transistor and an over current protection circuit (OCP). The OCP circuit includes an input device and a detection device. The input device is configured to receive a control signal and to generate a first voltage to a gate of the first group III nitride transistor. The detection device is configured to generate an output signal having a first logical value if a current at a drain of the first group III nitride transistor is less than a predetermined value and to generate the output signal having a second logical value if the current at the drain of the first group III nitride transistor is equal to or greater than the predetermined value, wherein the first logical value is different from the second logical value.Type: ApplicationFiled: May 20, 2020Publication date: November 24, 2022Inventors: JIANJIAN SHENG, YAOBIN GUAN
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Publication number: 20220375925Abstract: The present disclosure relates to a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a passivation layer covering the first gate conductor, and a second gate conductor disposed on the passivation layer and on a second region of the second nitride semiconductor layer, wherein the first region is laterally spaced apart from the second region.Type: ApplicationFiled: December 25, 2020Publication date: November 24, 2022Inventors: Danfeng MAO, King Yuen WONG, Jinhan ZHANG, Xiaoyan ZHANG, Wei WANG, Jianjian SHENG
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Publication number: 20220320077Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: Yaobin GUAN, Jianjian SHENG
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Patent number: 11398470Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).Type: GrantFiled: April 8, 2020Date of Patent: July 26, 2022Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Yaobin Guan, Jianjian Sheng
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CLAMPING CIRCUIT INTEGRATED ON GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND RELATED SEMICONDUCTOR DEVICE
Publication number: 20210210481Abstract: The present invention relates to a semiconductor device and a clamping circuit including a substrate; a first semiconductor layer, arranged on the substrate and composed of a III-nitride semiconductor material; a second semiconductor layer, arranged on the first semiconductor layer and composed of a III-nitride semiconductor material; a power transistor structure, including a gate structure, a drain structure and a source structure arranged on the second semiconductor layer; the first transistor structures, arranged on the second semiconductor layer; and the second transistor structures, arranged on the second semiconductor layer in series.Type: ApplicationFiled: April 28, 2020Publication date: July 8, 2021Inventors: Yaobin GUAN, Jianjian SHENG -
Publication number: 20200365581Abstract: The present disclosure provides an electrostatic protection circuit and an electronic device. The electrostatic protection circuit is connected to a first end point and a second end point of a power device. The electrostatic protection circuit is configured to allow bilateral electrostatic protection between the first end point and the second end point of the power device. The power device includes a transverse high-electron-mobility transistor (HEMT).Type: ApplicationFiled: April 8, 2020Publication date: November 19, 2020Inventors: Yaobin GUAN, Jianjian SHENG