Abstract: The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the present invention, a new higher bit address latching signal is added in order to latch the higher bit address so that an original lower bit address latching signal and the higher bit address latching signal can respectively latch the lower bit address and the higher bit address.

Abstract: A method for accessing image data and a method for accessing YUV420 image data are disclosed. The method for accessing image data uses two different approaches to a buffer for accessing the JPEG image data, so that the method can achieve instant JPEG image data compression with only one buffer.

Abstract: The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the present invention, a new higher bit address latching signal is added in order to latch the higher bit address so that an original lower bit address latching signal and the higher bit address latching signal can respectively latch the lower bit address and the higher bit address.

Abstract: A method for accessing image data and a method for accessing YUV420 image data are disclosed. The method for accessing image data uses two different approaches to a buffer for accessing the JPEG image data, so that the method can achieve instant JPEG image data compression with only one buffer.

Abstract: A digital camera with video input is disclosed. An image sensor is provided to capture an image and convert the captured image into R/G/B image signals the are processed by a video signal processing unit for being converted into pixel data having a first format. A TV decoder converts input analog video signals into pixel data having a second format. A scaling unit performs aspect ratio processing and zoom/pan function to pixel data. A TV interface unit converts pixel data having the second format into pixel data having the first format for being selectively output to the scaling unit directly and output to the scaling unit after transferring to the video signal processing unit for performing edge enhancement. A compressing and storage unit performs compress operation to the pixel data output from the video signal processing unit and the scaling unit. An USB unit converts pixel data after being compressed into serial data for output.

Abstract: A filtering circuit for image signal processing has a high frequency filtering circuit and a low frequency filtering circuit. The high frequency filtering circuit only includes one adder to obtain a high frequency component. The low frequency filtering circuit includes one adder and utilizes the high frequency component generated by the high frequency filtering circuit to obtain a low frequency component.