Patents by Inventor Jiann Liu
Jiann Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230400895Abstract: A swappable device includes a first side cover, a lever, a sliding plate, a functional module interface card and a second side cover. When the lever is rotated to move a guide pillar of the lever to a lower end point of an arc-shaped guide groove of the first side cover, a guide pillar of the sliding plate moves toward a rear end point of a linear guide groove of the lever and a lower end point of a linear guide groove of the first side cover. The sliding plate is actuated to drive the functional module interface card to move toward a lower edge of the first side cover relative to the first side cover until a plurality of connectors of the functional module interface card are at the farthest position relative to an upper edge of the first side cover.Type: ApplicationFiled: June 9, 2023Publication date: December 14, 2023Inventors: Shiang-Jiann LIU, Pin-Hsin KAO, Chung-Shin LIU
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Patent number: 6509218Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.Type: GrantFiled: April 9, 2002Date of Patent: January 21, 2003Assignee: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Hua-Chou Tseng, Jiann Liu
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Patent number: 6476448Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.Type: GrantFiled: January 12, 2001Date of Patent: November 5, 2002Assignee: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Hua-Chou Tseng, Jiann Liu
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Publication number: 20020110988Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.Type: ApplicationFiled: April 9, 2002Publication date: August 15, 2002Inventors: Wen-Kuan Yeh, Hua-Chou Tseng, Jiann Liu
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Publication number: 20020093054Abstract: The front-stage process of a fully depleted SOI device and the structure thereof are described. An SOI substrate having an insulation layer and a crystalline silicon layer above the insulation layer is provided. An isolation layer is formed in the crystalline silicon layer and is connected to the insulation layer to define a first-type MOS active region. An epitaxial suppressing layer is formed above the crystalline silicon layer outside of the first-type MOS active region. A second-type doped epitaxial silicon layer is selectively formed above the crystalline silicon layer in the first-type MOS active region. The second-type doped epitaxial layer is doped in-situ. An undoped epitaxial silicon layer is selectively formed above the second-type doped epitaxial silicon layer. The epitaxial suppressing layer is then removed.Type: ApplicationFiled: January 12, 2001Publication date: July 18, 2002Applicant: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Hua-Chou Tseng, Jiann Liu
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Patent number: 6323073Abstract: An SOI layer has a dielectric layer and a silicon layer formed on the dielectric layer. A shallow trench isolation structure is formed on the silicon layer. The STI structure passes through to the dielectric layer. A thermal diffusion process is performed to drive dopants into a first region of the silicon layer so as to form an N-well or P-well doped region. Next, a thermal diffusion process is performed to drive dopants into a second region of the silicon layer so as to form a P-well or N-well doped region. Finally, an epitaxy layer, having a thickness of about 200 angstroms, is grown on the surface of the silicon layer by way of a molecular-beam epitaxy (MBE) growth process, a liquid-phase epitaxy (LPE) growth process, or a vapor-phase epitaxy (VPE) growth process.Type: GrantFiled: January 19, 2001Date of Patent: November 27, 2001Assignee: United Microelectronics Corp.Inventors: Wen-Kuan Yeh, Hua-Chou Tseng, Jiann Liu
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Patent number: 6140705Abstract: A contact hole (32) is formed through a conducting layer (28). The conducting layer (28) is then undercut (34 and 36). An insulating layer (40) is formed in the contact hole (32). A contact (42) is then formed within the contact hole (32).Type: GrantFiled: January 3, 1995Date of Patent: October 31, 2000Assignee: Texas Instruments IncorporatedInventor: Jiann Liu
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Patent number: 6033975Abstract: A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).Type: GrantFiled: December 17, 1997Date of Patent: March 7, 2000Assignee: Texas Instruments IncorporatedInventors: Siang Ping Kwok, William F. Richardson, Dirk Noel Anderson, Jiann Liu
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Patent number: 6030861Abstract: A method for forming a dual-gate transistor includes the step of forming a gate oxide layer (18) over two transistor regions provided by a P-tank (12) and an N-tank (14). This is followed by depositing a layer of in-situ doped poly (20) and then masking off a portion of the poly layer (20) overlying the P-tank (12). This is then followed by diffusion of P-type impurities into the portion of the poly layer (20) overlying the N-tank (14) associated with the P-channel transistor. This is a process required for forming a DRAM memory. Utilizing the same oxide mask (22), a threshold implant is formed into the N-type (14).Type: GrantFiled: December 30, 1997Date of Patent: February 29, 2000Assignee: Texas Instruments IncorporatedInventor: Jiann Liu
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Patent number: 5956614Abstract: A process for forming a titanium disilicide conductive layer on the upper surface of a poly gate is implemented within a self-aligned contact process. In this process, the poly layer is first formed followed by sputtering thereon of a refractory metal layer such as titanium. This is then covered by a nitride or oxide capping layer (18). A gate electrode mesa is then formed which will then have a layer of oxide (26) deposited thereon by an LPCVD technique. The temperature of this oxide deposition is such that the refractory metal layer (16) will react with the underlying poly layer (14) to form a titanium disilicide layer (28). This requires the temperature to be in excess of 600.degree. C. for this step. Thereafter, the layer (26) will be utilized to form a sidewall spacer region.Type: GrantFiled: December 12, 1997Date of Patent: September 21, 1999Assignee: Texas Instruments IncorporatedInventor: Jiann Liu
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Patent number: 5671175Abstract: A DRAM array (100) having reduced bitline capacitance. The DRAM cell includes a pass transistor and a storage capacitor (150). An isolation structure (108) surrounds the DRAM cell. The bitline (140) is connected to a source/drain region (120b) of the pass transistor using a first polysilicon plug (112). A second polysilicon plug (110) connects the storage capacitor (150) to the other source/drain region (120a&c) of the pass transistor. Both polysilicon plugs (110, 112) extend through an interlevel dielectric layer (116) to one of the source/drain region (120a-c) of the pass transistor, but neither extends over the isolation structure (108). If desired, either the storage capacitor (150) or the bitline (140) may be offset from the source/drain regions (120a-c).Type: GrantFiled: June 26, 1996Date of Patent: September 23, 1997Assignee: Texas Instruments IncorporatedInventors: Jiann Liu, Clarence W. Teng
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Patent number: 5548548Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.Type: GrantFiled: December 19, 1994Date of Patent: August 20, 1996Assignee: Texas Instruments IncorporatedInventors: Amitava Chatterjee, Jiann Liu, Purnendu Mozumder, Mark S. Rodder, Ih-Chin Chen
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Patent number: 4818326Abstract: A processing apparatus and method for providing a process module with a low pressure, low energy ion implanter and a remote microwave plasma generator and a source of thermal energy, which is adapted to receive wafers for processing in a low pressure carrier.Type: GrantFiled: April 26, 1988Date of Patent: April 4, 1989Assignee: Texas Instruments IncorporatedInventors: Jiann Liu, Cecil J. Davis, Lee M. Loewenstein