Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a first carbon nanotube (CNT) layer on the dielectric layer at a first portion of the device corresponding to a first doping type, forming a second CNT layer on the dielectric layer at a second portion of the device corresponding to a second doping type, forming a plurality of first contacts on the first CNT layer, and a plurality of second contacts on the second CNT layer, performing a thermal annealing process to create end-bonds between the plurality of the first and second contacts and the first and second CNT layers, respectively, depositing a passivation layer on the plurality of the first and second contacts, and selectively removing a portion of the passivation layer from the plurality of first contacts.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: Variable-resistance devices and methods of forming the same include a variable-resistance layer, formed between a first terminal and a second terminal, that varies in resistance based on an oxygen concentration in the variable-resistance layer. An electrolyte layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage is positioned over the variable-resistance layer. A gate layer is configured to apply a voltage on the electrolyte layer and the variable-resistance layer and is positioned over the electrolyte layer.

Abstract: A combined nanofluidic and integrated circuit device includes a semiconductor wafer, which includes a substrate with active circuitry formed in the substrate; an oxide layer deposited adjacent the active circuitry; a stressor film deposited onto or into the oxide layer in sections, wherein the stressor film has a higher coefficient of thermal expansion than the oxide layer has; and a nanochannel formed in the oxide layer between the sections of the stressor film. According to an exemplary embodiment, the nanochannel is formed in the oxide layer by cooling the oxide layer and the stressor film to a fracture propagation temperature that is less than first and second temperatures at which the oxide layer and the stressor film are deposited on the substrate.

Abstract: A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.

Abstract: A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.

Abstract: A vertical transistor and a method of creating the same are provided. The vertical transistor has a substrate and a gate comprising a two-dimensional (2D) material on top of the substrate. There is a spacer on top of the gate. There is a gate dielectric comprising (i) a first portion on top of the spacer, (ii) a second portion extending down to a first side surface of the spacer and a side surface of the gate, and (iii) a third portion on top of the substrate. There is a channel comprising three portions. There is a first electrode on top of the first portion of the channel and a second electrode on top of the third portion of the channel.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: A drug delivery system includes a substrate, an integrated sensor disposed on the substrate, a drug delivery element disposed on the substrate, and a control unit coupled to the integrated sensor and the drug delivery element. The integrated sensor includes first and second electrodes disposed on a first surface of the substrate. The drug delivery element includes a reservoir disposed on the first surface of the substrate, a thermally active polymer enclosing the reservoir, and a heating coil disposed over the thermally active polymer. The control unit is configured to measure a biological parameter by measuring a voltage difference between the first and second electrodes of the integrated sensor, and to apply a trigger signal to the heating coil of the drug delivery element responsive to the measured biological parameter indicating a designated condition to heat up the thermally active polymer to selectively release a drug from the reservoir.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.

Abstract: A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Abstract: Chemical sensors include a functionalized electrode configured to change surface potential in the presence of an analyte. A piezoelectric element is connected to the functionalized electrode. A piezoresistive element is in contact with the piezoelectric element.

Abstract: Methods of using and making chemical sensors include exposing a functionalized electrode to a substance to be tested. The functionalized electrode is electrically connected to a sensor having a piezoelectric element and a piezoresistive element. A voltage on the functionalized electrode controls a resistance of the piezoresistive element. A current is measured passing through the piezoresistive element. The presence of the analyte is determined based on the measured current.

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the gate dielectric. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. The openings expose portions of the gate dielectric and end portions of the channel material under the patterned resist layer. Metal contacts are formed at least within the openings. The metal contacts include a portion that contacts the end portions of the channel material and the portions of the gate dielectric exposed within the openings.

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.

Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.

Abstract: Chemical sensors and methods of using and making the same include a functionalized electrode configured to change surface potential in the presence of an analyte. A piezoelectric element is connected to the functionalized electrode and is configured to change in volume in accordance with the surface potential of the functionalized electrode. A piezoresistive element is in contact with the piezoelectric element and is configured to change in resistance in accordance with the volume of the piezoelectric element.