Abstract: Disclosed herein are related to devices and methods for communication. In one aspect, a device includes a first processor and a second processor. The first processor may be configured to generate a first set of packets associated with an application data unit in a first layer corresponding to content data. Each packet of the first set of packets may include a flag indicative of an association with the application data unit. The second processor may be configured to generate a second set of one or more packets in a second layer for transmission, in response to determining that the first set of packets is associated with the application data unit according to flags of the first set of packets. The second processor may be configured to schedule to transmit the second set of one or more packets in the second layer within a defined time period.

Abstract: The present invention relates to a crystal form I of tenvermectin B, which can be characterized by X-ray powder diffraction (XRPD) pattern, Infrared (IR) absorption spectrum, Differential scanning calorimetry (DSC) thermogram and the like. Meanwhile, the present invention also relates to a method for preparing the crystal form I of tenvermectin B and a use thereof.

Abstract: Embodiments of the subject matter described herein relate to a wireless programmable media processing system. In the media processing system, a processing unit in a computing device generates a frame to be displayed based on a graphics content for an application running on the computing device. The frame to be displayed is then divided into a plurality of block groups which are compressed. The plurality of compressed block groups are sent to a graphics display device over a wireless link. In this manner, both the generation and the compression of the frame to be displayed may be completed at the same processing unit in the computing device, which avoids data copying and simplifies processing operations. Thereby, the data processing speed and efficiency is improved significantly.

Abstract: This application describes chiplet-based neuromorphic systems, devices, and chips. An exemplary chiplet-based neuromorphic system may include: a plurality of neuron processing entities (NPE); a plurality of chiplets each comprising a plurality of switches and a group of NPEs from the plurality of NPEs; and a plurality of interposers each comprising a plurality of routers and a group of chiplets from the plurality of chiplets; wherein each of the plurality of switches within each chiplet connects to one or more of the group of NPEs, and the plurality of switches within the each chiplet are organized in a tree topology; wherein each of the plurality of routers within each interposers connects to one or more of the group of chiplets, and the plurality of routers within the each interposer are organized in a tree topology.

Abstract: An autonomous construction robotic system is disclosed which includes a processing unit, a robotic arm, the robotic arm is adapted to be coupled to a central attachment arm and thereby position the central attachment arm according to a plurality of degrees of freedom, a panel handling and fastening system, including a panel handling assembly coupled to the central attachment arm and adapted to pick and place a construction panel onto a framed structure within a construction zone, and a vision system adapted to provide visual information to the processing unit associated with the framed structure, wherein the processing unit processes the visual information to automatically determine placement position of the construction panel on the framed structure.

Abstract: The present application discloses a calculator and a method thereof. The calculator is configured to accelerate the number-theoretic transformation of a 2N-dimensional polynomial. The calculator includes a first coefficient memory, a second coefficient memory, a twiddle factor memory, a plurality of processing units and a data flow controller. In the odd-number rounds of coefficient computation operations, the processing units perform first calculation procedures to read coefficients from the first coefficient memory for modulo calculation, and perform first writing procedures to write output coefficients to the second coefficient memory. In even-number rounds of coefficient computation operations, the processing units performs second calculation procedures to read coefficients from the second coefficient memory for modulo calculations, and perform second writing procedures to write output coefficients to the first coefficient memory.

Abstract: The present application discloses a computing accelerator, a data processor and an associated method for homomorphic encryption. The computing accelerator is configured to perform computations on input polynomials to generate output polynomials. The input polynomials are ciphertexts generated from a plaintext data after ring learning with error encryption, and the output polynomials correspond to a result after performing a linear computation on the plaintext data. The computing accelerator includes a polynomial multiplying unit, a coefficient extraction unit, and ciphertext wrapping unit. The polynomial multiplication unit multiplies a first input polynomial with a second input polynomial to generate an intermediate polynomial. The coefficient extraction unit converts the intermediate polynomial into a target polynomial according to a target coefficient in the intermediate polynomial. The ciphertext wrapping unit generates an output polynomial according to at least the target polynomial.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: An autonomous construction robotic system is disclosed which includes a processing unit, a robotic arm, the robotic arm is adapted to be coupled to a central attachment arm and thereby position the central attachment arm according to a plurality of degrees of freedom, a panel handling and fastening system, including a panel handling assembly coupled to the central attachment arm and adapted to pick and place a construction panel onto a framed structure within a construction zone, and a vision system adapted to provide visual information to the processing unit associated with the framed structure, wherein the processing unit processes the visual information to automatically determine placement position of the construction panel on the framed structure.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: Embodiments of the subject matter described herein relate to a wireless programmable media processing system. In the media processing system, a processing unit in a computing device generates a frame to be displayed based on a graphics content for an application running on the computing device. The frame to be displayed is then divided into a plurality of block groups which are compressed. The plurality of compressed block groups are sent to a graphics display device over a wireless link. In this manner, both the generation and the compression of the frame to be displayed may be completed at the same processing unit in the computing device, which avoids data copying and simplifies processing operations. Thereby, the data processing speed and efficiency is improved significantly.

Abstract: A method of generating a three-dimensional (3D) structure model from a two-dimensional (2D) drawing file, which includes one or more illustrations of a structure, using a data processing device includes importing the 2D drawing file to the data processing device, converting the 2D drawing file into a raster graphics file, converting the raster graphics file into a vector graphics file, extracting one or more graphical projections representative of the structure from the vector graphics file, converting the one or more projections into a tagged data graphics file, forming a 3D structure model representative of the structure by connecting the plurality of cartesian points of the tagged data graphics file, and generating an electronic output file including the 3D structure model.

Abstract: Embodiments of the subject matter described herein relate to a wireless programmable media processing system. In the media processing system, a processing unit in a computing device generates a frame to be displayed based on a graphics content for an application running on the computing device. The frame to be displayed is then divided into a plurality of block groups which are compressed. The plurality of compressed block groups are sent to a graphics display device over a wireless link. In this manner, both the generation and the compression of the frame to be displayed may be completed at the same processing unit in the computing device, which avoids data copying and simplifies processing operations. Thereby, the data processing speed and efficiency is improved significantly.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: An autonomous construction robotic system is disclosed which includes a processing unit, a robotic arm, the robotic arm is adapted to be coupled to a central attachment arm and thereby position the central attachment arm according to a plurality of degrees of freedom, a panel handling and fastening system, including a panel handling assembly coupled to the central attachment arm and adapted to pick and place a construction panel onto a framed structure within a construction zone, and a vision system adapted to provide visual information to the processing unit associated with the framed structure, wherein the processing unit processes the visual information to automatically determine placement position of the construction panel on the framed structure.

Abstract: A data-driven, object-oriented, and customizable method for visualizing a three-dimensional (3D) structure is disclosed which includes receiving a model-based data file including instantiation of elements of a structure, identifying one or more instances of one or more objects, providing data associated with the plurality of polygons for the object geometry to a visualization engine, providing data associated with the plurality of polygons for the object placement information to the visualization engine, providing data associated with the plurality of polygons for the object color and transparency information to the visualization engine, providing data associated with the plurality of polygons for the object functional information to the visualization engine, generating a 3D model of the object based on the plurality of polygons, and outputting a rendering of the 3D model for displaying on a digital display.

Abstract: The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.