Patents by Inventor Jiantan Liu

Jiantan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tiling format for convolutional neural networks
    Patent number: 11900253
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: February 13, 2024
    Assignee: Advanced Mic ro Devices, Inc.
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu
  • TILING FORMAT FOR CONVOLUTIONAL NEURAL NETWORKS
    Publication number: 20230186084
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 15, 2023
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu
  • Tiling format for convolutional neural networks
    Patent number: 11494592
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 8, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu
  • TILING FORMAT FOR CONVOLUTIONAL NEURAL NETWORKS
    Publication number: 20200394468
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu
  • Tiling format for convolutional neural networks
    Patent number: 10762392
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu
  • TILING FORMAT FOR CONVOLUTIONAL NEURAL NETWORKS
    Publication number: 20200202180
    Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
    Type: Application
    Filed: December 28, 2018
    Publication date: June 25, 2020
    Inventors: Song Zhang, Jiantan Liu, Hua Zhang, Min Yu