Patents by Inventor Jiantao Liu

Jiantao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11600220
    Abstract: The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: March 7, 2023
    Assignees: Hefei BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Tianxun Xiu, Changcheng Liu, Yanping Liao, Yinlong Zhang, Ming Deng, Guohuo Su, Jiantao Liu
  • Publication number: 20230043173
    Abstract: Provided is a touch display substrate. The touch display substrate includes a base substrate, including a display region and a non-display region; a plurality of touch electrodes disposed in the display region; and a plurality of signal transmission circuits, a plurality of first control lines, a plurality of second control lines, a target signal line, and a plurality of touch signal lines that are disposed in the non-display region.
    Type: Application
    Filed: August 4, 2021
    Publication date: February 9, 2023
    Inventors: Peng Liu, Peirong Huo, Hong Liu, Chao Liang, Aiyu Ding, Zhenhong Xiao, Yongqiang Zhang, Yusheng Liu, Jingyi Xu, Jiantao Liu, Bo Li
  • Publication number: 20230041917
    Abstract: An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 9, 2023
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiguo WANG, Jian SUN, Jiantao LIU, Xiaoyan YANG
  • Patent number: 11538487
    Abstract: The disclosure discloses a voice signal enhancing method and device, which divide a voice signal at the present scene into multiple frame signals based on a preset time interval; feed multiple frame signals into a trained neural network based on a preset step size, perform convolution operations on multiple frame signals through skip-connected convolutional layers to obtain multiple enhanced frame signals; superpose each enhanced frame signal according to the time domain of each enhanced frame signal to obtain an enhanced voice signal. Compared with the prior art, the present disclosure automatically enhances voice signals through the neural network without manual interference, so the effects and the application scenes of voice enhancement is not necessary to be limited by the preset method and method designers, thereby reducing the occurrence frequency of signal distortion and extra noises, which in turn improves the effects of the voice signal enhancement.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: December 27, 2022
    Assignee: YEALINK (XIAMEN) NETWORK TECHNOLOGY CO., LTD.
    Inventors: Wanjian Feng, Lianchang Zhang, Jiantao Liu
  • Publication number: 20220398968
    Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.
    Type: Application
    Filed: December 22, 2020
    Publication date: December 15, 2022
    Inventors: Zhen Wang, Jian Zhang, Jian Sun, Wei Yan, Deshuai Wang, Wenwen Qin, Jiguo Wang, Han Zhang, Yue Shan, Xiaoyan Yang, Yadong Zhang, Shijun Wang, Jiantao Liu
  • Publication number: 20220364711
    Abstract: The present disclosure provides a light strip, including a circuit board. A plurality of LEDs is arranged on the circuit board and spaced apart from each other in an extension direction of the circuit board, a positive connection end and a plurality of negative connection ends are arranged on the circuit board, and a plurality of LEDs is coupled between each negative connection end and the positive connection end. A plurality of LEDs between the first negative connection end and the positive connection end includes a head-end LED and a tail-end LED. The plurality of LEDs between the first negative connection end and the positive connection end includes a first LED and a second LED arranged at opposite sides of a first position in the extension direction of the circuit board. The present disclosure further provides a backlight module and a display module.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 17, 2022
    Inventors: Boning WANG, Gang LIU, Jian REN, Jiantao LIU, Li TIAN
  • Publication number: 20220367833
    Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate, the substrate comprising a blind hole area; a buffer layer covering one side of the substrate; an organic film layer provided on the surface of the buffer layer away from the substrate and having a first opening in the blind hole area; a passivation layer provided on the side of the organic film layer away from the substrate and having a second opening in the blind hole area; and a transparent electrode layer covering the passivation layer and the buffer layer in the second opening.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 17, 2022
    Inventors: Hong LIU, Jingyi XU, Yongqiang ZHANG, Peng LIU, Peirong HUO, Wanzhi CHEN, Xiaochun XU, Jiantao LIU, Bo LI
  • Publication number: 20220342527
    Abstract: A touch method, a touch circuit and a touch device are provided. The touch method includes: in an ath touch time period, providing a touch driving signal to an ath touch driving electrode; wherein a is a positive integer, a is less than or equal to A, and A is a positive integer; in an ath background data detection time period, providing a touch accompanying signal to N touch driving electrodes adjacent to the ath touch driving electrode; wherein N is a positive integer; and performing touch detection according to an ath touch sensing signal on touch sensing electrodes in the ath touch time period and an ath background data voltage signal on the touch sensing electrodes in the ath background data detection time period; wherein an amplitude of the touch accompanying signal is less than an amplitude of the touch driving signal.
    Type: Application
    Filed: September 25, 2020
    Publication date: October 27, 2022
    Inventors: Ning ZHU, Jian ZHAO, Peng JIANG, Jiantao LIU
  • Publication number: 20220342266
    Abstract: Provided are an array substrate and a display apparatus. The array substrate comprises: a base substrate; a gate line on the base substrate; a first insulating layer covering the gate line; a data line on the first insulating layer; a second insulating layer covering the data line; a common electrode on the second insulating layer, the common electrode comprising a plurality of portions, wherein each portion comprises a plurality of strip-shaped electrodes, each strip shaped electrode comprising a first main body portion, a second main body portion, a first connecting portion and a second connecting portion, and the first main body portion comprising a first corner end portion; and a metal wire in the same layer as the gate line, wherein an orthographic projection of the first corner end portion on the base substrate exceeds an orthographic projection of the metal wire on the base substrate.
    Type: Application
    Filed: May 12, 2021
    Publication date: October 27, 2022
    Inventors: Jingyong Hu, Zhe Li, Jingyu Wang, Jiantao Liu
  • Patent number: 11467450
    Abstract: An optical assembly, a liquid crystal display panel, and a display apparatus, the optical assembly including: a quarter-wave plate, a half-wave plate, and a linear polariser stacked in sequence; the direction of the absorption axis of the linear polariser, the direction of the slow axis of the half-wave plate and the quarter-wave plate are all parallel to the linear polariser; a first included angle between the direction of the absorption axis of the linear polariser and a first direction is 90°-100°; a second included angle between the direction of the slow axis of the half-wave plate and the first direction is 107°-114°; a third included angle between the direction of the slow axis of the quarter-wave plate and the first direction is 164°-176°.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: October 11, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Xuan Zhong, Hongliang Yuan, Jiantao Liu, Jian Wang, Donghua Zhang
  • Publication number: 20220317524
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate, and a display apparatus. The array substrate includes: a base substrate, a thin film transistor disposed on the base substrate; a first passivation layer, an organic film layer and a pixel electrode disposed on the thin film transistor; a connection structure for connecting the source electrode of the thin film transistor and the pixel electrode, wherein the connection structure is disposed in a via hole structure exposing the pixel electrode and the source electrode; or, the connection structure is disposed between the pixel electrode and the source electrode.
    Type: Application
    Filed: October 23, 2020
    Publication date: October 6, 2022
    Inventors: Yihe JIA, Xiangqian DING, Yongzhi SONG, Xiaoxiang ZHANG, Xiaolong LI, Lianjie YANG, Yan PANG, Jing LIU, Jiantao LIU
  • Publication number: 20220308409
    Abstract: The present disclosure relates to an array substrate, a liquid crystal display panel and a display device. The array substrate includes a base substrate on which a gate metal layer and a source-drain metal layer are stacked in sequence. The gate metal layer includes a plurality of independent gate lines and a plurality of independent dummy gates, the source-drain metal layer includes a plurality of independent data lines and a plurality of independent dummy drains. The dummy gate includes a main body portion in a pixel region defined by a gate line and a data line and a lead-out portion; and the dummy drains are in pixel regions, and the dummy drain in the pixel region includes a first subsection overlapping with the main body portion and a second subsection not overlapping with the main body portion.
    Type: Application
    Filed: September 21, 2020
    Publication date: September 29, 2022
    Inventors: Xuan ZHONG, Hongliang YUAN, Jian WANG, Qi ZHENG, Jiantao LIU, Yao BI, Hailong WANG, Lanjun GUO
  • Publication number: 20220308382
    Abstract: The present application proposes a display panel and a display device, the display panel includes a liquid crystal display module, a reflective film and a fingerprint identification module. The liquid crystal display module is on a first side of the reflective film, and the fingerprint identification module is on a second side of the reflective film opposite to the first side. The fingerprint identification module includes an invisible light emitting unit and an invisible light sensor. The invisible light emitting unit is configured to emit invisible light in a direction towards the reflective film, and the invisible light sensor is configured to receive reflected invisible light. The reflective film is configured to transmit the invisible light and reflect visible light reaching the reflective film through the liquid crystal display module.
    Type: Application
    Filed: January 26, 2021
    Publication date: September 29, 2022
    Inventors: Shubai ZHANG, Jiantao LIU, Haiwei SUN, Ming ZHAI, Yutao HAO, Litao FAN, Shuo WANG, Qin XIN, Zhiqiang ZHANG
  • Publication number: 20220302180
    Abstract: Embodiments of the disclosure provide a display substrate and a method for manufacturing the same. The display substrate includes: a base substrate; a thin film transistor including a source-drain metal layer and a first insulating layer; a second insulating layer; a color resist layer; and a third insulating layer. The third insulating layer comprises a first via hole that sequentially penetrates the third insulating layer, the color resist layer and the second insulating layer and thus extends from the third insulating layer to the source-drain metal layer. A sidewall of the first via hole comprises a first portion formed of a material of the second insulating layer, a second portion formed of a material of the color resist layer, and a third portion formed of a material of the third insulating layer, the second portion is between the first portion and the third portion.
    Type: Application
    Filed: October 29, 2021
    Publication date: September 22, 2022
    Inventors: Liang CHEN, Jincheng GAO, Haijiao QIAN, Tao JIANG, Zexu LIU, Tao WANG, Lixing ZHAO, Guanyong ZHANG, Quanzhou LIU, Jiantao LIU
  • Publication number: 20220301491
    Abstract: The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.
    Type: Application
    Filed: October 11, 2021
    Publication date: September 22, 2022
    Inventors: Tianxun XIU, Changcheng LIU, Yanping LIAO, Yinlong ZHANG, Ming DENG, Guohuo SU, Jiantao LIU
  • Publication number: 20220291558
    Abstract: A display panel and a display device are disclosed. The display panel comprises an array substrate and spacers; the array substrate comprises a first substrate, gate lines, data lines, and multiple sub-pixel units; the first substrate is provided with multiple sub-pixel regions, first wiring regions each located between two adjacent rows of sub-pixel regions, and second wiring regions each located between two adjacent columns of sub-pixel regions and intersecting the first wiring regions; at least part of each sub-pixel unit is located on a sub-pixel region; the gate lines and the data lines are respectively located on the first wiring regions and the second wiring regions and are electrically connected to the sub-pixel units; the data lines and the gate lines are insulated from each other and intersect each other; each data line is provided with an alignment part.
    Type: Application
    Filed: March 10, 2021
    Publication date: September 15, 2022
    Inventors: Qiujie SU, Xiaoyuan WANG, Zhihua SUN, Li TIAN, Seungmin LEE, Jiantao LIU
  • Publication number: 20220285406
    Abstract: The present disclosure provides a full-reflection display substrate, a manufacturing method thereof and a full-reflection display device. The full-reflection display substrate includes: a base substrate, the base substrate including a display region and a non-display region; a signal line arranged in the display region; a bonding pin arranged in the non-display region, coupled to the signal line and bonded to a driving circuitry; a reflection layer arranged in the display region; and an etch stop pattern arranged at a same layer and made of a same material as the reflection layer, arranged in the non-display region, and at least covering a side surface of the bonding pin.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 8, 2022
    Inventors: Jiguo WANG, Jian SUN, Jiantao LIU
  • Publication number: 20220283457
    Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate includes: a base substrate having a peripheral region, and thin film transistors disposed in the peripheral region of the base substrate. A gate electrode of the thin film transistor includes a plurality of sub-electrodes arranged at intervals.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 8, 2022
    Inventors: Feng LI, Yu MA, Qi SANG, Jiantao LIU, Li TIAN, Jing WANG
  • Publication number: 20220270560
    Abstract: A display driving circuit is provided. The display driving circuit includes a source driver, a temperature detecting circuit, and a timing control circuit, wherein the temperature detecting circuit is connected to the timing control circuit, and is configured to detect a temperature of the source driver; and the timing control circuit is further connected to the source driver, and is configured to output a source signal to the source driver based on the temperature of the source driver; wherein a magnitude of a voltage of the source signal is negatively related to the temperature of the source driver.
    Type: Application
    Filed: November 26, 2021
    Publication date: August 25, 2022
    Inventors: Ming DENG, Jiantao LIU, Zhihua SUN, Wenliang LIU
  • Publication number: 20220262289
    Abstract: A method for debugging the display panel includes: acquiring a target correction data table of the display panel in each of at least one color mode by debugging the display panel in each of the at least one color mode. Debugging the display panel in each of the at least one color mode includes: controlling the display panel to display a test picture in the color mode; acquiring an initial display parameter curve based on a display parameter of the test picture; determining a reference display parameter curve based on the initial display parameter curve and a standard display parameter curve; and determining the target correction data table based on the reference display parameter curve and the standard display parameter curve.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 18, 2022
    Inventors: Guohuo SU, Zhihua SUN, Jiantao LIU, Senwang LI, Zhun LIN, Wenliang LIU, Yinlong ZHANG, Jituo TANG, Jinling ZHANG